主页 时钟和计时 时钟缓冲器
主页
时钟和计时
时钟缓冲器

CDC509

正在供货

3.3V 相位锁定环路时钟驱动器

立即订购
数据表

CDC509

正在供货
数据表 立即订购

产品详情

Function Zero-delay Additive RMS jitter (typ) (fs) 200 Output frequency (max) (MHz) 125 Number of outputs 9 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 200 Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
Function Zero-delay Additive RMS jitter (typ) (fs) 200 Output frequency (max) (MHz) 125 Number of outputs 9 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 200 Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Use CDCVF2509A as a Replacement for this Device
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
  • Separate Output Enable for Each Output Bank
  • External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input
  • No External RC Network Required
  • Operates at 3.3-V VCC
  • Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package
  • Use CDCVF2509A as a Replacement for this Device
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
  • Separate Output Enable for Each Output Bank
  • External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input
  • No External RC Network Required
  • Operates at 3.3-V VCC
  • Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package

The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCC and is designed to drive up to five clock loads per output.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC509 is characterized for operation from 0°C to 70°C.

The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCC and is designed to drive up to five clock loads per output.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC509 is characterized for operation from 0°C to 70°C.
open-in-new 查找其他 时钟缓冲器
下载 观看带字幕的视频 视频

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 2
类型 标题 下载最新的英语版本 日期
* 数据表 CDC509: 3.3-V Phase-Lock Loop Clock Driver 数据表 (Rev. C) 2004年 12月 2日
应用手册 High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A) 1998年 9月 23日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

仿真模型

CDC509 IBIS Model

SCAC013.ZIP (2 KB) - IBIS Model
下载
模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
发送申请
封装 引脚 下载
TSSOP (PW) 24 查看选项
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频