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CDC351

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具有三态输出的 1 线至 10 线 3.3V 时钟驱动器

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数据表

CDC351

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产品详情

Function Single-ended Output frequency (max) (MHz) 100 Number of outputs 10 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 0.6 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
Function Single-ended Output frequency (max) (MHz) 100 Number of outputs 10 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 0.6 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 SSOP (DB) 24 63.96 mm² 8.2 x 7.8
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • LVTTL-Compatible Inputs and Outputs
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Distributes One Clock Input to Ten Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-32-mA IOH, 32-mA IOL)
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages

EPIC-IIB is a trademark of Texas Instruments Incorporated.
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • LVTTL-Compatible Inputs and Outputs
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Distributes One Clock Input to Ten Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-32-mA IOH, 32-mA IOL)
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages

EPIC-IIB is a trademark of Texas Instruments Incorporated.

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC.

The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC.

The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.
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* 数据表 1-Line To 10-Line Clock Driver With 3-State Outputs 数据表 (Rev. D) 2003年 6月 17日

设计和开发

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仿真模型

CDC351 IBIS Model

SCAC012.ZIP (7 KB) - IBIS Model
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SOIC (DW) 24 查看选项
SSOP (DB) 24 查看选项
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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