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超声波 AFE
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AFE5932

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64-channel tri-level receiver with no beamformer

数据表

AFE5932

正在供货
数据表

产品详情

Device type Receiver Number of input channels 32 Operating temperature range (°C) to Interface type LVDS Features Analog Front End (AFE) Rating Catalog
Device type Receiver Number of input channels 32 Operating temperature range (°C) to Interface type LVDS Features Analog Front End (AFE) Rating Catalog
  • AFE5932 supports:
    • 32-channels attenuator, PGA+LPF, 12-bit ADC, digital features with a decimation block
  • Input Attenuator (ATTEN) with DTGC
    • 24dB to 0dB attenuation range with 0.125dB step. Using in-built DTGC engine attenuation can be changed in real time.
  • Post-gain Amplifier (PGA) and low-pass filter LPF
    • Programmable gain of 12, 15 & 18 dB
    • Maximum output swing support 1.6 Vpp
    • LPF supported corners: First order filter with corner 10, 15 & 20 MHz
  • Analog to digital convertor
    • Maximum input swing support: 1.6 Vpp
    • Resolution: 12bit
    • Maximum ADC clock frequency (fADC_CLK): 50MHz
    • Full scale SNR: 62 dBFS
  • Decimation: Optional decimation block after ADC to decimate data by 2 or 4.
  • Compression block to combine data in fewer LVDS lanes as per the decimation factor
  • Total Power: 17 mW/ch at ADC Clock of 50MHz
  • Low speed CMOS serial programming interface to program front end and ADC upto 40MHz speed
  • Supply: 1.8V and 1.15V
  • Small package: FC-BGA-100 (10mm × 10mm) with 0.8mm pitch
  • AFE5932 supports:
    • 32-channels attenuator, PGA+LPF, 12-bit ADC, digital features with a decimation block
  • Input Attenuator (ATTEN) with DTGC
    • 24dB to 0dB attenuation range with 0.125dB step. Using in-built DTGC engine attenuation can be changed in real time.
  • Post-gain Amplifier (PGA) and low-pass filter LPF
    • Programmable gain of 12, 15 & 18 dB
    • Maximum output swing support 1.6 Vpp
    • LPF supported corners: First order filter with corner 10, 15 & 20 MHz
  • Analog to digital convertor
    • Maximum input swing support: 1.6 Vpp
    • Resolution: 12bit
    • Maximum ADC clock frequency (fADC_CLK): 50MHz
    • Full scale SNR: 62 dBFS
  • Decimation: Optional decimation block after ADC to decimate data by 2 or 4.
  • Compression block to combine data in fewer LVDS lanes as per the decimation factor
  • Total Power: 17 mW/ch at ADC Clock of 50MHz
  • Low speed CMOS serial programming interface to program front end and ADC upto 40MHz speed
  • Supply: 1.8V and 1.15V
  • Small package: FC-BGA-100 (10mm × 10mm) with 0.8mm pitch

The AFE5932 is a highly integrated, low power receiver device designed for portable ultrasound imaging systems. The device boasts a total of 32 receiver channels, each featuring an attenuator, PGA and low-pass filter, and ADC.

The AFE5932 is a highly integrated, low power receiver device designed for portable ultrasound imaging systems. The device boasts a total of 32 receiver channels, each featuring an attenuator, PGA and low-pass filter, and ADC.
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* 数据表 AFE5932, 32-Channel Ultrasound AFE With 17-mW/Channel Power, 2-nV/√Hz Noise, 12-Bit, 50-MSPS Output 数据表 PDF | HTML 2026年 3月 13日

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评估板

AFE5932EVM — AFE5932 评估模块

AFE5932EVM 用于评估 AFE5932 器件在各种模式下的性能。EVM 采用 2:1 多路复用配置，集成了两个 AFE5932 器件和两个 TX73L64 器件，可实现 128 通道发送和 64 通道接收。
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AFE5932-DESIGN — AFE5932 design resources

The full data sheet and other design resources for this device are available here
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