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  • MSP430FR25x2 电容式触摸感应混合信号微控制器

    • ZHCSHB4C January   2018  – December 2019 MSP430FR2512 , MSP430FR2522

      PRODUCTION DATA.  

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  • MSP430FR25x2 电容式触摸感应混合信号微控制器
  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1       Absolute Maximum Ratings
    2. 5.2       ESD Ratings
    3. 5.3       Recommended Operating Conditions
    4. 5.4       Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5       Active Mode Supply Current Per MHz
    6. 5.6       Low-Power Mode (LPM0) Supply Currents Into VCC Excluding External Current
    7. 5.7       Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8       Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9       Typical Characteristics - Low-Power Mode Supply Currents
    10. Table 5-1 Typical Characteristics – Current Consumption Per Module
    11. 5.10      Thermal Resistance Characteristics
    12. 5.11      Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. Table 5-2 PMM, SVS and BOR
      2. 5.11.2  Reset Timing
        1. Table 5-3 Wake-up Times From Low-Power Modes and Reset
      3. 5.11.3  Clock Specifications
        1. Table 5-4 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-5 DCO FLL, Frequency
        3. Table 5-6 DCO Frequency
        4. Table 5-7 REFO
        5. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-9 Module Oscillator (MODOSC)
      4. 5.11.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.11.4.1   Typical Characteristics – Outputs at 3 V and 2 V
      5. 5.11.5  VREF+ Built-in Reference
        1. Table 5-12 VREF+
      6. 5.11.6  Timer_A
        1. Table 5-13 Timer_A
      7. 5.11.7  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequency
        2. Table 5-15 eUSCI (UART Mode)
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode)
        5. Table 5-18 eUSCI (SPI Slave Mode)
        6. Table 5-19 eUSCI (I2C Mode)
      8. 5.11.8  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, 10-Bit Timing Parameters
        3. Table 5-22 ADC, 10-Bit Linearity Parameters
      9. 5.11.9  CapTIvate
        1. Table 5-23 CapTIvate Electrical Characteristics
        2. Table 5-24 CapTIvate Signal-to-Noise Ratio Characteristics
      10. 5.11.10 FRAM
        1. Table 5-25 FRAM
      11. 5.11.11 Debug and Emulation
        1. Table 5-26 JTAG, Spy-Bi-Wire Interface
        2. Table 5-27 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Standard Interface
    7. 6.7  Spy-Bi-Wire Interface (SBW)
    8. 6.8  FRAM
    9. 6.9  Memory Protection
    10. 6.10 Peripherals
      1. 6.10.1  Power-Management Module (PMM)
      2. 6.10.2  Clock System (CS) and Clock Distribution
      3. 6.10.3  General-Purpose Input/Output Port (I/O)
      4. 6.10.4  Watchdog Timer (WDT)
      5. 6.10.5  System (SYS) Module
      6. 6.10.6  Cyclic Redundancy Check (CRC)
      7. 6.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.10.8  Timers (Timer0_A3, Timer1_A3)
      9. 6.10.9  Hardware Multiplier (MPY)
      10. 6.10.10 Backup Memory (BAKMEM)
      11. 6.10.11 Real-Time Clock (RTC)
      12. 6.10.12 10-Bit Analog-to-Digital Converter (ADC)
      13. 6.10.13 CapTIvate Technology
      14. 6.10.14 Embedded Emulation Module (EEM)
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.11.2 Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors
    13. 6.13 Memory
      1. 6.13.1 Memory Organization
      2. 6.13.2 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
      2. 7.2.2 CapTIvate Peripheral
        1. 7.2.2.1 Device Connection and Layout Fundamentals
        2. 7.2.2.2 Measurements
          1. 7.2.2.2.1 SNR
          2. 7.2.2.2.2 Sensitivity
          3. 7.2.2.2.3 Power
    3. 7.3 CapTIvate Technology Evaluation
  8. 8器件和文档支持
    1. 8.1  入门和后续步骤
    2. 8.2  器件命名规则
    3. 8.3  工具和软件
    4. 8.4  文档支持
    5. 8.5  相关链接
    6. 8.6  社区资源
    7. 8.7  商标
    8. 8.8  静电放电警告
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9机械、封装和可订购信息
  10. 重要声明
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DATA SHEET

MSP430FR25x2 电容式触摸感应混合信号微控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 器件概述

1.1 特性

  • CapTIvate™ 技术 – 电容式触控
    • 性能
      • 两路同步快速电极扫描
      • 接近感应
    • 可靠性
      • 提高了针对电力线、射频及其他环境噪声的抗扰度
      • 内置扩展频谱、自动调优、噪声滤除和消抖算法
      • 提供可靠的触控解决方案，该方案具有 10V RMS 共模噪声、4kV 电气快速瞬变以及 15kV 静电放电，符合 IEC‑61000-4-6、IEC-61000-4-4 和 IEC‑61000-4-2 标准
      • 降低了射频辐射，简化了电气设计
      • 支持金属触控和防水设计
    • 灵活性
      • 多达 8 个自电容式电极和 16 个互电容式电极
      • 在同一设计中混合使用自电容式电极和互电容式电极
      • 支持多点触控功能
      • 宽电容检测范围；0 至 300pF 宽电极范围
    • 低功耗
      • 两个传感器的触摸唤醒电流小于 4µA
      • 触摸唤醒状态机支持在 CPU 休眠过程中进行电极扫描
      • 用于环境补偿、滤波和阈值检测的硬件加速
    • 易于使用
      • CapTIvate 设计中心，PC GUI 允许工程师对电容按钮进行实时设计和调试，无需编写代码
      • 存储于 ROM 中的 CapTIvate 软件库为客户应用提供充足的 FRAM
  • 嵌入式微控制器
    • 16 位 RISC 架构
    • 支持的时钟频率最高可达 16MHz
    • 3.6V 至 1.8V 的宽电源电压范围（最低电源电压受限于 SVS 电平，请参阅 SVS 规格）
  • 优化的超低功耗模式
    • 激活模式：120µA/MHz（典型值）
    • 待机模式：两个传感器的触摸唤醒电流小于 4µA
    • 关断模式 (LPM4.5)：36nA，无 SVS
  • 低功耗铁电 RAM (FRAM)
    • 非易失性存储器容量高达 7.5KB
    • 内置错误修正码 (ECC)
    • 可配置的写保护
    • 对程序、常量和存储的统一存储
    • 耐写次数达 1015 次
    • 抗辐射和非磁性
    • FRAM 与 SRAM 之比高达 4：1
  • 高性能模拟
    • 高达 8 通道 10 位模数转换器 (ADC)
      • 1.5V 的内部基准电压
      • 采样与保持 200ksps
  • 智能数字外设
    • 两个 16 位计时器，每个计时器有三个捕捉/比较寄存器 (Timer_A3)
    • 一个 16 位计时器，采用 CapTIvate™技术
    • 一个仅用作计数器的 16 位 RTC
    • 16 位循环冗余校验 (CRC)
  • 增强型串行通信，支持引脚重映射功能（请参阅器件比较）
    • 一个 eUSCI_A 接口，支持 UART、IrDA 和 SPI
    • 一个 eUSCI_B 接口，支持 SPI 和 I2C
  • 时钟系统 (CS)
    • 片上 32kHz RC 振荡器 (REFO)
    • 带有锁频环 (FLL) 的片上 16MHz 数控振荡器 (DCO)
      • 室温下的精度为 ±1%（具有片上基准）
    • 片上超低频 10kHz 振荡器 (VLO)
    • 片上高频调制振荡器 (MODOSC)
    • 外部 32kHz 晶振 (LFXT)
    • 可编程 MCLK 预分频器（1 至 128）
    • 通过可编程预分频器（1、2、4 或 8）从 MCLK 获得的 SMCLK
  • 通用输入/输出和引脚功能
    • 共计 15 个 I/O（采用 VQFN-20 封装）
    • 15 个中断引脚（P1 和 P2）可以将 MCU 从低功耗模式下唤醒
  • 开发工具和软件
    • 开发工具
      • MSP CapTIvate™ MCU 开发套件评估：与 CAPTIVATE‑PGMR 编程器和电容式触控 MSP430FR2522 MCU 板 BOOSTXL‑CAPKEYPAD 配合使用
      • 目标开发板 MSP‑TS430RHL20
    • 易于使用的生态系统
      • CapTIvate 设计中心 – 代码生成、可自定义 GUI、实时调优
  • 12KB ROM 库包含 CapTIvate 触控程序库和驱动程序库
  • 系列成员（另请参阅器件特性）
    • MSP430FR2522：7.25KB 程序 FRAM、256B 信息 FRAM、2KB RAM
      ，多达 8 个自电容式传感器和 16 个互电容式传感器
    • MSP430FR2512：7.25KB 程序 FRAM、256B 信息 FRAM、2KB RAM
      ，多达 4 个自电容式传感器或互电容式传感器
  • 封装选项
    • 20 引脚：VQFN (RHL)
    • 16 引脚：TSSOP (PW)

1.2 应用

  • 电子智能锁、门键盘和读取器
  • 车库门系统
  • 入侵 HMI 键盘和控制面板
  • 电梯呼叫按钮
  • 个人电子产品
  • 无线扬声器和耳机
  • A/V 接收器
  • 电器
  • 电动工具
  • 照明开关
  • 可视门铃

1.3 说明

MSP430FR25x2 包含一系列用于电容式触摸传感的超低功耗 MSP430™微控制器 (MCU)，它们均采用 CapTIvate™ 触控技术，适用于 应用 采用1到16个电容式按钮或接近感应的成本敏感型应用。MSP430FR25x2 MCU 适用于 应用 电磁干扰、油液、水和油脂影响的工业应用，可以创造价值，实现高性能。这些器件可提供 IEC 认证的解决方案，其功耗比同类竞争解决方案低 5 倍且支持接近感应以及透过玻璃、塑料和金属镀层进行触摸操作。

TI 电容式触摸感应 MSP430 MCU 由一套全面的硬件和软件生态系统进行支持，并配套提供参考设计和代码示例，协助用户快速开展设计。BOOSTXL-CAPKEYPADBoosterPack™插件模块可搭配使用 CAPTIVATE-PGMR 编程器电路板（单独使用或作为 MSP-CAPT-FR2633 CapTIvate 开发套件的一部分），或 LaunchPad 开发套件生态系统。TI 还提供免费的软件，如 CapTIvate 设计中心，工程师可以在其中 借助 方便易用的 GUI 和 ™MSP430Ware™ 软件以及包括 CapTIvate 技术指南在内的综合性文档快速进行应用开发。

采用 CapTIvate 技术的 MSP430 MCU 提供市面上集成度和自主性领先的电容式触控解决方案，可在最低功耗下实现高可靠性和抗噪能力。有关更多信息，请访问 ti.com.cn/captivate。

有关完整的模块说明，请参阅《MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南》。

器件信息(1)

器件型号 封装 封装尺寸(2)
MSP430FR2522IPW16 TSSOP (16) 5mm x 4.4mm
MSP430FR2522IRHL VQFN (20) 4.5mm x 3.5mm
MSP430FR2512IPW16 TSSOP (16) 5mm x 4.4mm
MSP430FR2512IRHL VQFN (20) 4.5mm x 3.5mm
(1) 要获得最新的产品、封装和订购信息，请参见封装选项附录（Section 9），或者访问德州仪器 (TI) 网站 www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（Section 9中）。

CAUTION

系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范，以防发生电气过载或对数据或代码存储器造成干扰。有关更多信息，请参阅《MSP430 系统级 ESD 注意事项》。

1.4 功能框图

Figure 1-1 给出了功能框图。

MSP430FR2522 MSP430FR2512 SLASEE4_Functional_Block_Diagram.gifFigure 1-1 功能框图
  • MCU 的主电源对 DVCC 和 DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为 4.7μF 至 10μF 和 0.1μF，精度为 ±5%。
  • VREG 是 CapTIvate 稳压器的去耦电容。所需去耦电容的建议值为 1µF，最大等效串联电阻 (ESR) ≤ 200mΩ。
  • P1 和 P2 特有引脚中断功能，可将 MCU 从所有低功耗模式 (LPM) 唤醒（包括 LPM3.5 和 LPM4）。
  • 每个 Timer_A3 具有三个捕捉/比较寄存器。仅 CCR1 和 CCR2 从外部连接。CCR0 寄存器仅用于内部周期时序和生成中断。
  • 在 LPM3 或 LPM4 模式下，CapTIvate 模块可以正常工作，而其他外设则会关闭。

2 修订历史记录

从修订版本 B 更改为修订版本 C

Changes from August 20, 2019 to December 10, 2019

  • Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 5.3, Recommended Operating ConditionsGo
  • Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to Table 5-4, XT1 Crystal Oscillator (Low Frequency)Go
  • Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-4, XT1 Crystal Oscillator (Low Frequency)Go
  • Corrected the test conditions for the RI parameter in Table 5-20, ADC, Power Supply and Input Range ConditionsGo
  • Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-21, ADC, 10-Bit Timing ParametersGo
  • Added "1.5-V reference factor" in Table 6-18, Device DescriptorsGo
  • Changed the CRC covered end address to 0x1AF5 in note (1) in Table 6-18, Device DescriptorsGo

Changes from November 8, 2018 to August 19, 2019

  • 更新了Section 1.1特性Go
  • Changed CapTIvate BSWP demonstration board to CapTIvate phone demonstration board in note (11) on Section 5.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External CurrentGo
  • Changed CapTIvate BSWP demonstration board to CapTIvate phone demonstration board in note (19) on Section 5.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External CurrentGo
  • Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate Electrical CharacteristicsGo
  • Added test condition for CELECTRODE in Table 5-23 , CapTIvate Electrical CharacteristicsGo
  • Changed the symbol and description of the DCCAPCLK parameter in Table 5-23, CapTIvate Electrical CharacteristicsGo
  • Moved the SNR parameter to Table 5-24, CapTIvate Signal-to-Noise Ratio CharacteristicsGo
  • Updated Section 7.2.2, CapTIvate PeripheralGo
  • 更新了Section 8.2，器件命名规则Go

Changes from January 12, 2018 to November 7, 2018

  • 删除了Section 1.1，特性 中“接近感应”项的“15cm”Go
  • 更改了 Section 1.1，特性 中的列表项“3.6V 至 1.8V 的宽电源电压范围...”Go
  • Updated Section 3.1, Related ProductsGo
  • Changed HBM limit to ±1000 V and CDM limit to ±250 V in Section 5.2, ESD RatingsGo
  • Changed the MIN value of the VCC parameter from 2 V to 1.8 V in Section 5.3, Recommended Operating ConditionsGo
  • Changed the crystal in the footnote that begins "Characterized with a Seiko Crystal SC-32S crystal..." in Section 5.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External CurrentGo
  • Changed the crystal in the footnote that begins "Characterized with a Seiko Crystal SC-32S crystal..." in Section 5.8, Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External CurrentGo
  • Added note on VSVSH- and VSVSH+ parameters to Table 5-2, PMM, SVS and BORGo
  • Changed the minimum VCC from 2.0 V to 1.8 V in the test conditions for the fREFO, dfREFO/ dVCC, and fDC parameters and in note (2) in Table 5-7, REFOGo
  • Changed the minimum VCC from 2.0 V to 1.8 V in the test conditions for the dfVLO/dVCC parameter and in note (2) in Table 5-8, Internal Very-Low-Power Low-Frequency Oscillator (VLO)Go
  • Changed the minimum VCC from 2.0 V to 1.8 V in the test conditions for the fMODOSC/dVCC parameter in Table 5-9, Module Oscillator (MODOSC)Go
  • Added the SNR parameter in Table 5-23, CapTIvate Electrical CharacteristicsGo
  • Corrected bitfield from RTCCLK to RTCCKSEL in table note that starts "Controlled by ..." in Table 6-8, Clock DistributionGo
  • Corrected bitfield from IRDSEL to IRDSSEL in Section 6.10.8, Timers (Timer0_A3, Timer1_A3), in the description that starts "The interconnection of Timer0_A3 and ..."Go
  • Corrected ADCINCHx column heading in Table 6-13, ADC Channel ConnectionsGo
  • Added P1SELC information in Table 6-28, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added P2SELC information in Table 6-28, Port P1, P2 Registers (Base Address: 0200h)Go

3 Device Comparison

Table 3-1 summarizes the features of the available family members.

Table 3-1 Device Comparison(1)(2)

DEVICE PROGRAM FRAM + INFORMATION FRAM (bytes) SRAM (bytes) TA0,TA1 eUSCI_A eUSCI_B 10-BIT ADC CHANNELS CapTIvate TECHNOLOGY CHANNELS GPIOs PACKAGE
MSP430FR2522IRHL 7424 + 256 2048 2, 3 × CCR(3) 1 1 8 8 15 20 RHL (VQFN)
MSP430FR2522IPW16 7424 + 256 2048 2, 3 × CCR(3) 1 1 5 8 11 16 PW (TSSOP)
MSP430FR2512IRHL 7424 + 256 2048 2, 3 × CCR(3) 1 1 8 4 15 20 RHL (VQFN)
MSP430FR2512IPW16 7424 + 256 2048 2, 3 × CCR(3) 1 1 5 4 11 16 PW (TSSOP)
(1) For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging
(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM outputs.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers

High-performance, low-power solutions to enable the autonomous future

Products for MSP430 ultra-low-power sensing and measurement microcontrollers

One platform. One ecosystem. Endless possibilities.

Companion Products for MSP430FR2522

Review products that are frequently purchased or used in conjunction with this product.

Reference Designs

Find reference designs leveraging the best in TI technology to solve your system-level challenges

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the 20-pin RHL package.

MSP430FR2522 MSP430FR2512 SLASEE4_PINOUT_QFN20-FR2522.gif

NOTE:

CAP1.x are available only on MSP430FR2522 device and NOT available on MSP430FR2512 device.
Figure 4-1 20-Pin RHL Package (Top View)

Figure 4-2 shows the pinout for the 16-pin PW package.

MSP430FR2522 MSP430FR2512 SLASEE4__PINOUT_TSSOP16-FR2522.gif

NOTE:

CAP1.x are available only on MSP430FR2522 device and NOT available on MSP430FR2512 device.
Figure 4-2 16-Pin PW Package (Top View)

4.2 Pin Attributes

Table 4-1 lists the attributes of all pins.

Table 4-1 Pin Attributes

PIN NUMBER SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE(5) RESET STATE AFTER BOR(6)
RHL PW16
1 1 P1.1 (RD) I/O LVCMOS DVCC OFF
UCB0CLK I/O LVCMOS DVCC –
ACLK I/O LVCMOS DVCC –
CAP1.1(7) I/O Analog VREG –
A1 I Analog DVCC –
VREF+ I Analog Power –
2 2 P1.0 (RD) I/O LVCMOS DVCC OFF
UCB0STE I/O LVCMOS DVCC –
CAP1.0(7) I/O Analog VREG –
A0 I Analog DVCC –
Veref+ I Analog Power –
3 3 TEST (RD) I LVCMOS DVCC OFF
SBWTCK I LVCMOS DVCC –
4 4 RST (RD) I LVCMOS DVCC OFF
NMI I LVCMOS DVCC –
SBWTDIO I/O LVCMOS DVCC –
5 5 DVCC P Power DVCC N/A
6 6 DVSS P Power DVCC N/A
7 7 P2.1 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC –
UCA0SOMI I/O LVCMOS DVCC –
XIN I LVCMOS DVCC –
8 8 P2.0 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC –
UCA0SIMO I/O LVCMOS DVCC –
XOUT O LVCMOS DVCC –
9 – P2.6 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC –
UCB0SCL I/O LVCMOS DVCC –
10 – P2.5 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC –
UCB0SDA I/O LVCMOS DVCC –
A7 I Analog DVCC –
11 – P2.4 (RD) I/O LVCMOS DVCC OFF
TA1CLK I LVCMOS DVCC –
UCB0CLK I/O LVCMOS DVCC –
A6 I Analog DVCC –
12 – P2.3 (RD) I/O LVCMOS DVCC OFF
TA1.2 I/O LVCMOS DVCC –
UCB0STE I/O LVCMOS DVCC –
A5 I Analog DVCC –
13 9 P2.2 (RD) I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC –
SYNC I LVCMOS DVCC –
A4 I Analog DVCC –
14 10 P1.7 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC –
TDO O LVCMOS DVCC –
CAP0.3 I/O Analog VREG –
15 11 P1.6 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC –
TA0CLK I LVCMOS DVCC –
TDI I LVCMOS DVCC –
TCLK I LVCMOS DVCC –
CAP0.2 I/O Analog VREG –
16 12 P1.5 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC –
UCA0SOMI I/O LVCMOS DVCC –
TA0.2 I/O LVCMOS DVCC –
TMS I LVCMOS DVCC –
CAP0.1 I/O Analog VREG –
17 13 P1.4 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC –
UCA0SIMO I/O LVCMOS DVCC –
TA0.1 I/O LVCMOS DVCC –
TCK I LVCMOS DVCC –
CAP0.0 I/O Analog VREG –
18 14 VREG P Power VREG N/A
19 15 P1.3 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC –
UCB0SCL I/O LVCMOS DVCC –
MCLK O LVCMOS DVCC –
CAP1.3(7) I/O Analog VREG –
A3 I Analog DVCC –
20 16 P1.2 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC –
UCB0SDA I/O LVCMOS DVCC –
SMCLK O LVCMOS DVCC –
CAP1.2(7) I/O Analog VREG –
A2 I Analog DVCC –
Veref- I Analog Power –
(1) Signals names with (RD) denote the reset default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output
(3) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3)
(4) To determine the pin mux encodings for each pin, see Section 6.11.
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Reset States:
OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled
N/A = Not applicable
(7) MSP430FR2522 only

 
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