ZHCSQS0E August   2006  – January 2024 TPS5410

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information 
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Oscillator Frequency
      2. 6.3.2  Voltage Reference
      3. 6.3.3  Enable (ENA) and Internal Slow-Start
      4. 6.3.4  Undervoltage Lockout (UVLO)
      5. 6.3.5  Boost Capacitor (BOOT)
      6. 6.3.6  Output Feedback (VSENSE)
      7. 6.3.7  Internal Compensation
      8. 6.3.8  Voltage Feed-Forward
      9. 6.3.9  Pulse-Width-Modulation (PWM) Control
      10. 6.3.10 Overcurrent Limiting
      11. 6.3.11 Overvoltage Protection
      12. 6.3.12 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Minimum Input Voltage
      2. 6.4.2 ENA Control
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application Circuit
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Switching Frequency
          2. 7.2.1.2.2 Input Capacitors
          3. 7.2.1.2.3 Output Filter Components
            1. 7.2.1.2.3.1 Inductor Selection
            2. 7.2.1.2.3.2 Capacitor Selection
          4. 7.2.1.2.4 Output Voltage Setpoint
          5. 7.2.1.2.5 Boot Capacitor
          6. 7.2.1.2.6 Catch Diode
          7. 7.2.1.2.7 Advanced Information
            1. 7.2.1.2.7.1 Output Voltage Limitations
            2. 7.2.1.2.7.2 Internal Compensation Network
            3. 7.2.1.2.7.3 Thermal Calculations
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Using All Ceramic Capacitors
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Output Filter Capacitor Selection
          2. 7.2.2.2.2 External Compensation Network
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.1.3 Application Curves

The performance graphs in Figure 7-2 to Figure 7-9 are applicable to the circuit in Figure 7-1. TA = 25 °C. unless otherwise specified.

GUID-F515CB12-03D0-4F58-93DA-943A1776C403-low.gifFigure 7-2 Efficiency vs Output Current
GUID-7F7591B4-A3FE-4EC5-A993-30AF385BA4AC-low.gifFigure 7-4 Output Voltage Regulation % vs Input Voltage
GUID-1762C034-A1C2-4F15-823B-B5925E9D58A1-low.gifFigure 7-6 Output Voltage Ripple and PH Node, IO = 1 A
GUID-A17C0FB3-4FAC-43F2-82A5-DB23887206B5-low.gifFigure 7-8 Start-up Waveform, VI and VO
GUID-964161D0-E8C9-495C-B1DA-227C53EE7370-low.gifFigure 7-3 Output Voltage Regulation % vs Output Current
GUID-D166F950-E20F-4A7B-A245-17C30F75EF19-low.gifFigure 7-5 Input Voltage Ripple and PH Node, IO = 1 A
GUID-979586FB-BCFD-4CE3-A8CE-804BC33E6DC4-low.gifFigure 7-7 Transient Response, IO Step 0.25 to 0.75 A
GUID-CB9032F8-9E68-4B49-98DE-3AF49EEC4120-low.gifFigure 7-9 Start-up Waveform, ENA and VO