ZHCSQC3C April   2019  – January 2025 DLP470TE

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Capacitance at Recommended Operating Conditions
    8. 5.8  Timing Requirements
      1. 5.8.1 Timing Diagrams
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 DMD Die Temperature Sensing
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
        1. 9.2.3.1 Voltage Signals
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
    2. 10.2 第三方产品免责声明
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
      2. 10.3.2 支持资源
      3. 10.3.3 Receiving Notification of Documentation Updates
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.2 Impedance Requirements

TI recommends that the board has matched impedance of 50Ω ±10% for all signals. The exceptions are listed in Table 9-2.

Table 9-2 Special Impedance Requirements
Signal Type Signal Name Impedance (ohms)
A channel LVDS differential pairsD_AP(0:15), D_AN(0:15)100 ±10% differential across each pair
DCLKA_P, DCLKA_N
SCTRL_AP, SCTRL_AN
B channel LVDS differential pairsD_BP(0:15), D_BN(0:15)100 ±10% differential across each pair
DCLKB_P, DCLKB_N
SCTRL_BP, SCTRL_BN
C channel LVDS differential pairs D_CP(0:15), D_CN(0:15)100 ±10% differential across each pair
DCLKC_P, DCLKC_N
SCTRL_CP, SCTRL_CN
D channel LVDS differential pairs D_DP(0:15), D_DN(0:15)100 ±10% differential across each pair
DCLKD_P, DCLKD_N
SCTRL_DP, SCTRL_DN