ZHCSNQ2C March   2021  – January 2024 AWR1843AOP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1. 3.1 功能方框图
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Pin Functions - Digital and Analog [ALP Package]
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Supply Specifications
    6. 6.6  Power Consumption Summary
    7. 6.7  RF Specification
    8. 6.8  CPU Specifications
    9. 6.9  Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1  Antenna Radiation Patterns
        1. 6.10.1.1 Antenna Radiation Patterns for Receiver
        2. 6.10.1.2 Antenna Radiation Patterns for Transmitter
      2. 6.10.2  Antenna Positions
      3. 6.10.3  Power Supply Sequencing and Reset Timing
      4. 6.10.4  Input Clocks and Oscillators
        1. 6.10.4.1 Clock Specifications
      5. 6.10.5  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 6.10.5.1 Peripheral Description
        2. 6.10.5.2 MibSPI Transmit and Receive RAM Organization
          1. 6.10.5.2.1 SPI Timing Conditions
          2. 6.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 6.10.5.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 6.10.5.3 SPI Peripheral Mode I/O Timings
          1. 6.10.5.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 6.10.5.4 Typical Interface Protocol Diagram (Slave Mode)
      6. 6.10.6  LVDS Interface Configuration
        1. 6.10.6.1 LVDS Interface Timings
      7. 6.10.7  General-Purpose Input/Output
        1. 6.10.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-4685AB93-A014-47EA-9F05-952FFC28DBFA/T4362547-45 #GUID-4685AB93-A014-47EA-9F05-952FFC28DBFA/T4362547-50
      8. 6.10.8  Controller Area Network Interface (DCAN)
        1. 6.10.8.1 Dynamic Characteristics for the DCANx TX and RX Pins
      9. 6.10.9  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 6.10.9.1 Dynamic Characteristics for the CANx TX and RX Pins
      10. 6.10.10 Serial Communication Interface (SCI)
        1. 6.10.10.1 SCI Timing Requirements
      11. 6.10.11 Inter-Integrated Circuit Interface (I2C)
        1. 6.10.11.1 I2C Timing Requirements #GUID-64613E7E-5DDF-4B01-8FA0-13739060F368/T4362547-185
      12. 6.10.12 Quad Serial Peripheral Interface (QSPI)
        1. 6.10.12.1 QSPI Timing Conditions
        2. 6.10.12.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6A95C194-2C40-46FE-9793-4574200DA2C4/T4362547-210 #GUID-6A95C194-2C40-46FE-9793-4574200DA2C4/T4362547-209
        3. 6.10.12.3 QSPI Switching Characteristics
      13. 6.10.13 ETM Trace Interface
        1. 6.10.13.1 ETMTRACE Timing Conditions
        2. 6.10.13.2 ETM TRACE Switching Characteristics
      14. 6.10.14 Data Modification Module (DMM)
        1. 6.10.14.1 DMM Timing Requirements
      15. 6.10.15 JTAG Interface
        1. 6.10.15.1 JTAG Timing Conditions
        2. 6.10.15.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 6.10.15.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Subsystems
      1. 7.3.1 RF and Analog Subsystem
        1. 7.3.1.1 Clock Subsystem
        2. 7.3.1.2 Transmit Subsystem
        3. 7.3.1.3 Receive Subsystem
      2. 7.3.2 Processor Subsystem
      3. 7.3.3 Automotive Interface
      4. 7.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 7.3.5 DSP Subsystem Memory Map
    4. 7.4 Other Subsystems
      1. 7.4.1 ADC Channels (Service) for User Application
        1. 7.4.1.1 GP-ADC Parameter
  9. 8 Monitoring and Diagnostics
    1. 8.1 Monitoring and Diagnostic Mechanisms
      1. 8.1.1 Error Signaling Module
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Reference Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
6.10.5.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)
NO.(1)(2)(3) PARAMETER MIN TYP MAX UNIT
1 tc(SPC)M Cycle time, SPICLK(4) 25 256tc(VCLK) ns
2(4) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 ns
tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4
3(4) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 ns
tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4
4(4) td(SPCH-SIMO)M Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0) 0.5tc(SPC)M – 3 ns
td(SPCL-SIMO)M Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1) 0.5tc(SPC)M – 3
5(4) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0) 0.5tc(SPC)M – 10.5 ns
tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1) 0.5tc(SPC)M – 10.5
6(5) tC2TDELAY Setup time CS active until SPICLK high
(clock polarity = 0)		 CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY + 2)*tc(VCLK) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5 ns
CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY + 2)*tc(VCLK) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5
Setup time CS active until SPICLK low
(clock polarity = 1)		 CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY+2)*tc(VCLK) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5
CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY+3)*tc(VCLK) – 7 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) + 7.5
7(5) tT2CDELAY Hold time, SPICLK low until CS inactive (clock polarity = 0) (T2CDELAY + 1) *tc(VCLK) – 7.5 (T2CDELAY + 1) *tc(VCLK) + 7 ns
Hold time, SPICLK high until CS inactive (clock polarity = 1) (T2CDELAY + 1) *tc(VCLK) – 7.5 (T2CDELAY + 1) *tc(VCLK) + 7
8(4) tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low
(clock polarity = 0)		 5 ns
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high
(clock polarity = 1)		 5
9(4) th(SPCL-SOMI)M Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)		 3 ns
th(SPCH-SOMI)M Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)		 3
(1) The Controller bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).
(2) tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
GUID-6A6051CA-597B-42FA-BA69-77A213936CC3-low.gif Figure 6-10 SPI Controller Mode External Timing (CLOCK PHASE = 1)
GUID-0D966465-F3AA-4189-B6B9-BD329F855EEC-low.gif Figure 6-11 SPI Controller Mode Chip Select Timing (CLOCK PHASE = 1)