本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。
LMG3522R030-Q1 GaN FET 具有集成式驱动器和保护功能,适用于开关模式电源转换器,可让设计人员实现更高水平的功率密度和效率。
LMG3522R030-Q1 集成了一个硅驱动器,可实现高达 150V/ns 的开关速度。与分立式硅栅极驱动器相比,TI 的集成式精密栅极偏置可实现更高的开关 SOA。这种集成特性与 TI 的低电感封装技术相结合,可在硬开关电源拓扑中提供干净的开关和超小的振铃。可调栅极驱动强度允许将压摆率控制在 20V/ns 至 150V/ns 之间,这可用于主动控制 EMI 并优化开关性能。
高级电源管理功能包括数字温度报告和故障检测。GaN FET 的温度通过可变占空比 PWM 输出进行报告,这可简化器件加载管理。报告的故障包括过热、过流和 UVLO 监控。
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
NC1 | 1, 16 | — | Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to DRAIN. |
DRAIN | 2–15 | P | GaN FET drain. Internally connected to NC1. |
NC2 | 17, 27, 43, 47, 52 | — | Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to SOURCE and THERMAL PAD. |
SOURCE | 18–26, 28–39 | P | GaN FET source. Internally connected to NC2 and THERMAL PAD. |
VNEG | 40, 41 | P | Internal buck-boost converter negative output. Used as the negative supply to turn off the depletion mode GaN FET. Bypass to SOURCE with a 2.2-µF capacitor. |
BBSW | 42 | P | Internal buck-boost converter switch pin. Connect an inductor from this point to SOURCE. |
VDD | 44 | P | Device input supply. |
IN | 45 | I | CMOS-compatible non-inverting input used to turn the FET on and off. |
FAULT | 46 | O | Push-pull digital output that asserts low during a fault condition. Refer to Fault Detection for details. |
OC | 48 | O | Push-pull digital output that asserts low during overcurrent and short-circuit fault conditions. Refer to Fault Detection for details. |
TEMP | 49 | O | Push-pull digital output that gives information about the GaN FET temperature. Outputs a fixed 9-kHz pulsed waveform. The device temperature is encoded as the duty cycle of the waveform. |
RDRV | 50 | I | Drive-strength selection pin. Connect a resistor from this pin to SOURCE to set the turn-on drive strength to control slew rate. Tie the pin to SOURCE to enable 150 V/ns and tie the pin to LDO5V to enable 100 V/ns. |
LDO5V | 51 | P | 5-V LDO output for external digital isolator. If using this externally, connect a 0.1-µF or greater capacitor to SOURCE. |
THERMAL PAD | — | — | Thermal pad. Internally connected to SOURCE and NC2. |