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  • 具有集成驱动器、保护和温度报告功能的 LMG3522R030-Q1 650V 30mΩ GaN FET

    • ZHCSNE5D October   2020  – February 2024 LMG3522R030-Q1

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  • 具有集成驱动器、保护和温度报告功能的 LMG3522R030-Q1 650V 30mΩ GaN FET
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Switching Parameters
      1. 6.1.1 Turn-On Times
      2. 6.1.2 Turn-Off Times
      3. 6.1.3 Drain-Source Turn-On Slew Rate
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN FET Operation Definitions
      2. 7.3.2  Direct-Drive GaN Architecture
      3. 7.3.3  Drain-Source Voltage Capability
      4. 7.3.4  Internal Buck-Boost DC-DC Converter
      5. 7.3.5  VDD Bias Supply
      6. 7.3.6  Auxiliary LDO
      7. 7.3.7  Fault Detection
        1. 7.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 7.3.7.2 Overtemperature Shutdown
        3. 7.3.7.3 UVLO Protection
        4. 7.3.7.4 Fault Reporting
      8. 7.3.8  Drive-Strength Adjustment
      9. 7.3.9  Temperature-Sensing Output
      10. 7.3.10 Ideal-Diode Mode Operation
        1. 7.3.10.1 Overtemperature-Shutdown Ideal-Diode Mode
    4. 7.4 Start-Up Sequence
    5. 7.5 Safe Operation Area (SOA)
      1. 7.5.1 Repetitive SOA
    6. 7.6 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Slew Rate Selection
          1. 8.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 8.2.2.2 Signal Level-Shifting
        3. 8.2.2.3 Buck-Boost Converter Design
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Using an Isolated Power Supply
      2. 8.4.2 Using a Bootstrap Diode
        1. 8.4.2.1 Diode Selection
        2. 8.4.2.2 Managing the Bootstrap Voltage
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Solder-Joint Reliability
        2. 8.5.1.2 Power-Loop Inductance
        3. 8.5.1.3 Signal-Ground Connection
        4. 8.5.1.4 Bypass Capacitors
        5. 8.5.1.5 Switch-Node Capacitance
        6. 8.5.1.6 Signal Integrity
        7. 8.5.1.7 High-Voltage Spacing
        8. 8.5.1.8 Thermal Recommendations
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 Export Control Notice
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
  13. 重要声明
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Data Sheet

具有集成驱动器、保护和温度报告功能的 LMG3522R030-Q1 650V 30mΩ GaN FET

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

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1 特性

  • 符合面向汽车应用的 AEC-Q100 标准
    • 温度等级 1：–40°C 至 +125°C，TA
    • 结温：–40°C 至 +150°C，TJ
  • 带集成栅极驱动器的 650V GaN-on-Si FET
    • 集成高精度栅极偏置电压
    • 200V/ns FET 释抑
    • 2MHz 开关频率
    • 20V/ns 至 150V/ns 压摆率，用于优化开关性能和缓解 EMI
    • 由 7.5V 至 18V 电源供电
  • 强大的保护
    • 响应时间 < 100ns 的逐周期过流和锁存短路保护
    • 硬开关时可承受 720V 浪涌
    • 针对内部过热和 UVLO 监控的自我保护
  • 高级电源管理
    • 数字温度 PWM 输出
  • 顶部冷却 12mm × 12mm VQFN 封装将电气路径和散热路径分开，可实现超低的电源环路电感

2 应用

  • 开关模式电源转换器
  • 商用网络和服务器 PSU
  • 商用通信电源整流器
  • 车载充电器 (OBC) 和无线充电器
  • 直流/直流转换器
GUID-56727E62-3C5A-489B-87F9-87E74F3E3739-low.gif 简化版方框图

3 说明

LMG3522R030-Q1 GaN FET 具有集成式驱动器和保护功能，适用于开关模式电源转换器，可让设计人员实现更高水平的功率密度和效率。

LMG3522R030-Q1 集成了一个硅驱动器，可实现高达 150V/ns 的开关速度。与分立式硅栅极驱动器相比，TI 的集成式精密栅极偏置可实现更高的开关 SOA。这种集成特性与 TI 的低电感封装技术相结合，可在硬开关电源拓扑中提供干净的开关和超小的振铃。可调栅极驱动强度允许将压摆率控制在 20V/ns 至 150V/ns 之间，这可用于主动控制 EMI 并优化开关性能。

高级电源管理功能包括数字温度报告和故障检测。GaN FET 的温度通过可变占空比 PWM 输出进行报告，这可简化器件加载管理。报告的故障包括过热、过流和 UVLO 监控。

封装信息
器件型号 封装(1) 封装尺寸(2)
LMG3522R030-Q1 RQS（VQFN，52） 12.00mm x 12.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。
GUID-20220511-SS0I-TTVC-W9BZ-WLXVDCQWX2WC-low.svg>100V/ns 时的开关性能

4 Pin Configuration and Functions

Figure 4-1 RQS Package,52-Pin VQFN(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
NC1 1, 16 — Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to DRAIN.
DRAIN 2–15 P GaN FET drain. Internally connected to NC1.
NC2 17, 27, 43, 47, 52 — Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to SOURCE and THERMAL PAD.
SOURCE 18–26, 28–39 P GaN FET source. Internally connected to NC2 and THERMAL PAD.
VNEG 40, 41 P Internal buck-boost converter negative output. Used as the negative supply to turn off the depletion mode GaN FET. Bypass to SOURCE with a 2.2-µF capacitor.
BBSW 42 P Internal buck-boost converter switch pin. Connect an inductor from this point to SOURCE.
VDD 44 P Device input supply.
IN 45 I CMOS-compatible non-inverting input used to turn the FET on and off.
FAULT 46 O Push-pull digital output that asserts low during a fault condition. Refer to Fault Detection for details.
OC 48 O Push-pull digital output that asserts low during overcurrent and short-circuit fault conditions. Refer to Fault Detection for details.
TEMP 49 O Push-pull digital output that gives information about the GaN FET temperature. Outputs a fixed 9-kHz pulsed waveform. The device temperature is encoded as the duty cycle of the waveform.
RDRV 50 I Drive-strength selection pin. Connect a resistor from this pin to SOURCE to set the turn-on drive strength to control slew rate. Tie the pin to SOURCE to enable 150 V/ns and tie the pin to LDO5V to enable 100 V/ns.
LDO5V 51 P 5-V LDO output for external digital isolator. If using this externally, connect a 0.1-µF or greater capacitor to SOURCE.
THERMAL PAD — — Thermal pad. Internally connected to SOURCE and NC2.
(1) I = input, O = output, P = power

5 Specifications

5.1 Absolute Maximum Ratings

Unless otherwise noted: voltages are in respect to SOURCE connected to reference ground(1)
MIN MAX UNIT
VDS Drain-source voltage, FET off 650 V
VDS(surge) Drain-source voltage, FET switching, surge condition(2) 720 V
VDS,tr Drain-source transient ringing peak voltage, FET off, surge condition(2)(3) 800 V
Pin voltage VDD –0.3 20 V
LDO5V –0.3 5.5 V
VNEG –16 0.5 V
BBSW VVNEG–1 VVDD+0.5 V
IN –0.3 20 V
FAULT, OC, TEMP –0.3 VLDO5V+0.3 V
RDRV –0.3 5.5 V
ID(RMS) Drain RMS current, FET on 55 A
ID(pulse) Drain pulsed current, FET on, tp < 10 µs(4) –125 Internally limited A
IS(pulse) Source pulsed current, FET off, tp < 1 µs 80 A
TJ Operating junction temperature(5) –40 150 °C
TSTG Storage temperature –55 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) See Section 7.3.3 for an explanation of the switching cycle drain-source voltage ratings.
(3) t1 < 200 ns in Figure 7-1.
(4) The positive pulsed current must remain below the overcurrent threshold to avoid the FET being automatically shut off. The FET drain intrinsic positive pulsed current rating for tp < 10 µs is 120 A.
(5) Refer to the Electrical and Switching Characteristics Tables for junction temperature test conditions.

5.2 ESD Ratings

PARAMETER VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100–002(3) ±2000 V
Charged-device model (CDM), per AEC Q100–011 All pins ±500
Corner pins (1, 16, 17, 26, 27, 42, 43, and 52) ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

5.3 Recommended Operating Conditions

Unless otherwise noted: voltages are in respect to SOURCE connected to reference ground.
MIN NOM MAX UNIT
Supply voltage VDD
(Maximum switching frequency derated for VVDD < 9 V)		 7.5 12 18 V
Input voltage IN 0 5 18 V
ID(RMS) Drain RMS current 38 A
Positive source current LDO5V 25 mA
RRDRV RDRV to SOURCE resistance from external slew-rate control resistor 0 500 kΩ
CVNEG VNEG to SOURCE capacitance from external bypass capacitor 1 10 µF
LBBSW BBSW to SOURCE inductance from external buck-boost inductor (1) 3 4.7 10 µH
(1) > 1-A current rating is recommended.

5.4 Thermal Information

THERMAL METRIC(1) LMG3522R030 UNIT
RQS (VQFN)
52 PINS
RθJC(top) Junction-to-case (top) thermal resistance 0.28 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are in respect to SOURCE connected with reference ground; –40 ℃ ≤ TJ ≤ 125 ℃;
VDS = 520 V; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V;  LBBSW = 4.7 µH
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER TRANSISTOR
RDS(on) Drain-source on resistance VIN = 5 V, TJ = 25°C 26 35 mΩ
VIN = 5 V, TJ = 125°C 45 mΩ
VSD Third-quadrant mode source-drain voltage IS = 0.1 A 3.6 V
IS = 20 A 3 5 V
IDSS Drain leakage current VDS = 650 V, TJ = 25°C 1 µA
VDS = 650 V, TJ = 125°C 10 µA
COSS Output capacitance VDS = 400 V 235 pF
CO(er) Energy related effective output capacitance VDS = 0 V to 400 V 320 pF
CO(tr) Time related effective output capacitance 460 pF
QOSS Output charge 190 nC
QRR Reverse recovery charge 0 nC
VDD – SUPPLY CURRENTS
VDD quiescent current VVDD = 12 V, VIN = 0 V or 5 V 700 1200 µA
VDD operating current VVDD = 12 V, fIN  = 140 kHz, soft-switching 15.5 20 mA
BUCK BOOST CONVERTER
VNEG output voltage VNEG sinking 50 mA –14 V
IBBSW,PK(low) Peak BBSW sourcing current at low peak current mode setting
(peak external buck-boost inductor current)		 0.3 0.4 0.5 A
IBBSW,PK(high) Peak BBSW sourcing current at low peak current mode setting
(peak external buck-boost inductor current)		 0.8 1 1.2 A
High peak current mode setting enable – IN positive-going threshold frequency 280 420 515 kHz
LDO5V
Output voltage LDO5V sourcing 25 mA 4.75 5 5.25 V
Short-circuit current 25 50 100 mA
IN
VIN,IT+ Positive-going input threshold voltage 1.7 1.9 2.45 V
VIN,IT– Negative-going input threshold voltage 0.7 1.0 1.3 V
Input threshold hysteresis 0.7 0.9 1.3 V
Input pulldown resistance VIN = 2 V 100 150 200 kΩ
FAULT, OC/ZVD, TEMP – OUPUT DRIVE
Low-level output voltage Output sinking 8 mA 0.16 0.4 V
High-level output voltage Output sourcing 8 mA, measured as
VLDO5V – VO		 0.2 0.45 V
VDD, VNEG – UNDER VOLTAGE LOCKOUT
VVDD,T+(UVLO) VDD UVLO – positive-going threshold voltage 6.4 7 7.6 V
VDD UVLO – negative-going threshold voltage 6 6.5 7.1 V
VDD UVLO – input threshold voltage hysteresis 510 mV
VNEG UVLO – negative-going threshold voltage –13.6 –13.0 –12.3 V
VNEG UVLO – positive-going threshold voltage –13.3 –12.75 –12.1 V
GATE DRIVER
Turn-on slew rate From VDS < 320 V to VDS < 80 V, RDRV disconnected from LDO5V, RRDRV = 300 kΩ, TJ = 25℃, VBUS = 400 V, LHB current = 10 A, see Figure 6-1   20 V/ns
From VDS < 320 V to VDS < 80 V, RDRV tied to LDO5V, TJ = 25℃, VBUS = 400 V, LHB current = 10 A, see Figure 6-1    90 V/ns
From VDS < 320 V to VDS < 80 V, RDRV disconnected from LDO5V, RRDRV = 0 Ω, TJ = 25℃, VBUS = 400 V, LHB current = 10 A, see Figure 6-1         150 V/ns
Maximum GaN FET switching frequency. VNEG rising to > –13.25 V, soft-switched, maximum switching frequency derated for VVDD < 9 V  2 MHz
FAULTS
IT(OC) DRAIN overcurrent fault – threshold current 60 70 80 A
IT(SC) DRAIN short-circuit fault – threshold current 75 90 105 A
di/dtT(SC) di/dt threshold between overcurrent and short-circuit faults 150 A/µs
GaN temperature fault – postive-going threshold temperature 175 °C
GaN temperature fault – threshold temperature hysteresis 30 °C
Driver temperature fault – positive-going threshold temperature 185 °C
Driver temperature fault – threshold temperature hysteresis 20 °C
TEMP
Output frequency 4.3 9 14 kHz
Output PWM duty cycle GaN TJ = 150℃ 82 %
GaN TJ = 125℃ 58.5 64.6 70 %
GaN TJ = 85℃ 36.2 40 43.7 %
GaN TJ = 25℃ 0.03 3 6 %
IDEAL-DIODE MODE CONTROL
VT(3rd) Drain-source third-quadrant detection – threshold voltage –0.15 0 0.15 V
IT(ZC) Drain zero-current detection – threshold current 0℃ ≤ TJ ≤ 125℃ –0.2 0 0.2 A
–40°C ≤ TJ ≤ 0°C –0.35 0 0.35 A

5.6 Switching Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to SOURCE connected with reference ground; –40 ℃ ≤ TJ ≤ 125 ℃; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V;  LBBSW = 4.7 µH
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING TIMES
td(on)(Idrain) Drain-current turn-on delay time From VIN > VIN,IT+ to ID > 1 A, VBUS = 400 V, LHB current = 10 A, see Figure 6-1 and Figure 6-2        28 42 ns
td(on) Turn-on delay time  From VIN > VIN,IT+ to VDS < 320 V, VBUS = 400 V, LHB current = 10 A, see Figure 6-1 and Figure 6-2    33 54 ns
tr(on) Turn-on rise time From VDS < 320 V to VDS < 80 V, VBUS = 400 V, LHB current = 10 A, see Figure 6-1 and Figure 6-2        2.8 4.3 ns
td(off) Turn-off delay time  From VIN < VIN,IT– to VDS > 80 V, VBUS = 400 V, LHB current = 10 A, see Figure 6-1 and Figure 6-2      48 69 ns
tf(off) Turn-off fall time(1) From VDS > 80 V to VDS > 320 V, VBUS = 400 V, LHB current = 10 A, see Figure 6-1 and Figure 6-2        22 ns
Minimum IN high pulse-width for FET turn-on VIN rise/fall times < 1 ns, VDS falls to < 200 V, VBUS = 400 V, LHB current = 10 A, see Figure 6-1   24 ns
STARTUP TIMES
t(start) Driver start-up time From VVDD > VVDD,T+(UVLO) to FAULT high, CLDO5V = 100 nF, CVNEG = 2.2 µF at 0-V bias linearly decreasing to 1.5 µF at 15-V bias 310 470 µs
FAULT TIMES
toff(OC) Overcurrent fault FET turn-off time, FET on before overcurrent VIN = 5 V, From ID > IT(OC) to ID < 50 A, ID di/dt = 100 A/µs 115 170 ns
toff(SC) Short-circuit current fault FET turn-off time, FET on before short circuit VIN = 5 V, From ID > IT(SC) to ID < 50 A, ID di/dt = 700 A/µs 65 100 ns
Overcurrent fault FET turn-off time, FET turning on into overcurrent From ID > IT(OC) to ID < 50 A 200 250 ns
Short-circuit fault FET turn-off time, FET turning on into short circuit From ID > IT(SC) to ID < 50 A 80 180 ns
IN reset time to clear FAULT latch From VIN < VIN,IT– to FAULT high 250 380 580 µs
t(window)(OC) Overcurrent fault to short-circuit fault window time 50 ns
IDEAL-DIODE MODE CONTROL TIMES
Ideal-diode mode FET turn-on time VDS < VT(3rd) to FET turn-on, VDS being discharged by half-bridge configuration inductor at 5 A 50 65 ns
Ideal-diode mode FET turn-off time ID > IT(ZC) to FET turn-off, ID di/dt = 100 A/µs created with a half-bridge configuration 55 76 ns
Overtemperature-shutdown ideal-diode mode IN falling blanking time  150 230 360 ns
(1) During turn-off, VDS rise time is the result of the resonance of COSS and loop inductance as well as load current.

5.7 Typical Characteristics

GUID-20221006-SS0I-VJ28-RGKG-VDZZ4Q9TKVZM-low.svgFigure 5-1 Drain-Current Turn-On Delay Time vs Drive-Strength Resistance
GUID-20221007-SS0I-2JR8-KT6N-JXTWTXFH97ZV-low.svgFigure 5-3 Turn-On Rise Time vs Drive-Strength Resistance
GUID-20221011-SS0I-SC9L-MRNN-GT12GC24KJ95-low.svg
 
Figure 5-5 Drain Current vs Drain-Source Voltage
GUID-20221011-SS0I-J1LQ-814K-6DWMCC8NSX73-low.svgFigure 5-7 Normalized On-Resistance vs Junction Temperature
GUID-20221011-SS0I-H2D7-NFS5-MBDZ8KD5KW4M-low.svg
VDD = 12 V TJ = 25°C
Figure 5-9 VDD Supply Current vs IN Switching Frequency
GUID-20221006-SS0I-DPPZ-XDTV-K5SVNRJCH9F2-low.svgFigure 5-11 Repetitive Safe Operation Area
GUID-20221006-SS0I-PQQL-JW8G-Q6BSNRPN7JLM-low.svgFigure 5-2 Turn-On Delay Time vs Drive-Strength Resistance
GUID-20221006-SS0I-M419-KSX8-FVXF1TC7L7VH-low.svgFigure 5-4 Turn-On Slew Rate vs Drive-Strength Resistance
GUID-20221011-SS0I-CM1W-ZVQZ-0S2BLN229NJ6-low.svg
IN = 0 V
Figure 5-6 Off-State Source-Drain Voltage vs Source Current
GUID-20221007-SS0I-3LDV-BP2L-FLVBXHZRWSDL-low.svgFigure 5-8 Output Capacitance vs Drain-Source Voltage
GUID-20221011-SS0I-VLCD-MSP0-LMN9K6TG6LWL-low.svg
VDD = 12 V TJ = 125°C
Figure 5-10 VDD Supply Current vs IN Switching Frequency

6 Parameter Measurement Information

6.1 Switching Parameters

Figure 6-1 shows the circuit used to measure most switching parameters. The top device in this circuit is used to re-circulate the inductor current and functions in third-quadrant mode only. The bottom device is the active device that turns on to increase the inductor current to the desired test current. The bottom device is then turned off and on to create switching waveforms at a specific inductor current. Both the drain current (at the source) and the drain-source voltage is measured. Figure 6-2 shows the specific timing measurement. TI recommends to use the half-bridge as a double pulse tester. Excessive third-quadrant operation can overheat the top device.

GUID-20221012-SS0I-CRZX-89M7-LX6PWWCDQWFK-low.svg Figure 6-1 Circuit Used to Determine Switching Parameters
GUID-20221012-SS0I-3B2W-TW6M-8ZJKWT8BFTGS-low.svg Figure 6-2 Measurement to Determine Propagation Delays and Slew Rates

6.1.1 Turn-On Times

The turn-on transition has three timing components: drain-current turn-on delay time, turn-on delay time, and turn-on rise time. The drain-current turn-on delay time is from when IN goes high to when the GaN FET drain-current reaches 1 A. The turn-on delay time is from when IN goes high to when the drain-source voltage falls 20% below the bus voltage. Finally, the turn-on rise time is from when drain-source voltage falls 20% below the bus voltage to when the drain-source voltage falls 80% below the bus voltage. Note that the turn-on rise time is the same as the VDS 80% to 20% fall time. All three turn-on timing components are a function of the RDRV pin setting.

6.1.2 Turn-Off Times

The turn-off transition has two timing components: turn-off delay time, and turn-off fall time. The turn-off delay time is from when IN goes low to when the drain-source voltage rises to 20% of the bus voltage. The turn-off fall time is from when the drain-source voltage rises to 20% of the bus voltage to when the drain-source voltage rises to 80% of the bus voltage. Note that the turn-off fall time is the same as the VDS 20% to 80% rise time. The turn-off timing components are independent of the RDRV pin setting, but heavily dependent on the LHB load current.

 
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