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  • LMX2694-EP 具有相位同步功能的 15GHz 宽带 PLLatinum 射频合成器

    • ZHCSKL5D November   2019  – March 2022 LMX2694-EP

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  • LMX2694-EP 具有相位同步功能的 15GHz 宽带 PLLatinum 射频合成器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Reference Path
        1. 7.3.2.1 OSCIN Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Post-R Divider (PLL_R)
      3. 7.3.3  State Machine Clock
      4. 7.3.4  PLL Phase Detector and Charge Pump
      5. 7.3.5  N Divider and Fractional Circuitry
      6. 7.3.6  MUXOUT Pin
        1. 7.3.6.1 Serial Data Output for Readback
        2. 7.3.6.2 Lock Detect Indicator Set as Type “VCOCal”
        3. 7.3.6.3 Lock Detect Indicator Set as Type “Vtune and VCOCal”
      7. 7.3.7  VCO (Voltage-Controlled Oscillator)
        1. 7.3.7.1 VCO Calibration
        2. 7.3.7.2 Determining the VCO Gain
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Buffer
      10. 7.3.10 Powerdown Modes
      11. 7.3.11 Treatment of Unused Pins
      12. 7.3.12 Phase Synchronization
        1. 7.3.12.1 General Concept
        2. 7.3.12.2 Categories of Applications for SYNC
        3. 7.3.12.3 Procedure for Using SYNC
        4. 7.3.12.4 SYNC Input Pin
      13. 7.3.13 Phase Adjust
      14. 7.3.14 Fine Adjustments for Phase Adjust and Phase SYNC
      15. 7.3.15 SYSREF
        1. 7.3.15.1 Programmable Fields
        2. 7.3.15.2 Input and Output Pin Formats
          1. 7.3.15.2.1 SYSREF Output Format
        3. 7.3.15.3 SYSREF Examples
        4. 7.3.15.4 SYSREF Procedure
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power-Up Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1   R0 Register (Offset = 0x0) [reset = 0x200C]
      2. 7.6.2   R1 Register (Offset = 0x1) [reset = 0x80C]
      3. 7.6.3   R2 Register (Offset = 0x2) [reset = 0x500]
      4. 7.6.4   R3 Register (Offset = 0x3) [reset = 0x642]
      5. 7.6.5   R4 Register (Offset = 0x4) [reset = 0xA43]
      6. 7.6.6   R5 Register (Offset = 0x5) [reset = 0xC8]
      7. 7.6.7   R6 Register (Offset = 0x6) [reset = 0xC802]
      8. 7.6.8   R7 Register (Offset = 0x7) [reset = 0xB2]
      9. 7.6.9   R8 Register (Offset = 0x8) [reset = 0x2000]
      10. 7.6.10  R9 Register (Offset = 0x9) [reset = 0x604]
      11. 7.6.11  R10 Register (Offset = 0xA) [reset = 0x10F8]
      12. 7.6.12  R11 Register (Offset = 0xB) [reset = 0x18]
      13. 7.6.13  R12 Register (Offset = 0xC) [reset = 0x5001]
      14. 7.6.14  R13 Register (Offset = 0xD) [reset = 0x4000]
      15. 7.6.15  R14 Register (Offset = 0xE) [reset = 0x1E70]
      16. 7.6.16  R15 Register (Offset = 0xF) [reset = 0x64F]
      17. 7.6.17  R16 Register (Offset = 0x10) [reset = 0x80]
      18. 7.6.18  R17 Register (Offset = 0x11) [reset = 0x96]
      19. 7.6.19  R18 Register (Offset = 0x12) [reset = 0x64]
      20. 7.6.20  R19 Register (Offset = 0x13) [reset = 0x27B7]
      21. 7.6.21  R20 Register (Offset = 0x14) [reset = 0x3048]
      22. 7.6.22  R21 Register (Offset = 0x15) [reset = 0x401]
      23. 7.6.23  R22 Register (Offset = 0x16) [reset = 0x1]
      24. 7.6.24  R23 Register (Offset = 0x17) [reset = 0x7C]
      25. 7.6.25  R24 Register (Offset = 0x18) [reset = 0x71A]
      26. 7.6.26  R25 Register (Offset = 0x19) [reset = 0x624]
      27. 7.6.27  R26 Register (Offset = 0x1A) [reset = 0xDB0]
      28. 7.6.28  R27 Register (Offset = 0x1B) [reset = 0x2]
      29. 7.6.29  R28 Register (Offset = 0x1C) [reset = 0x488]
      30. 7.6.30  R29 Register (Offset = 0x1D) [reset = 0x318C]
      31. 7.6.31  R30 Register (Offset = 0x1E) [reset = 0x318C]
      32. 7.6.32  R31 Register (Offset = 0x1F) [reset = 0xC3EC]
      33. 7.6.33  R32 Register (Offset = 0x20) [reset = 0x393]
      34. 7.6.34  R33 Register (Offset = 0x21) [reset = 0x1E21]
      35. 7.6.35  R34 Register (Offset = 0x22) [reset = 0x10]
      36. 7.6.36  R35 Register (Offset = 0x23) [reset = 0x4]
      37. 7.6.37  R36 Register (Offset = 0x24) [reset = 0x70]
      38. 7.6.38  R37 Register (Offset = 0x25) [reset = 0x205]
      39. 7.6.39  R38 Register (Offset = 0x26) [reset = 0xFFFF]
      40. 7.6.40  R39 Register (Offset = 0x27) [reset = 0xFFFF]
      41. 7.6.41  R40 Register (Offset = 0x28) [reset = 0x0]
      42. 7.6.42  R41 Register (Offset = 0x29) [reset = 0x0]
      43. 7.6.43  R42 Register (Offset = 0x2A) [reset = 0x0]
      44. 7.6.44  R43 Register (Offset = 0x2B) [reset = 0x0]
      45. 7.6.45  R44 Register (Offset = 0x2C) [reset = 0x22A2]
      46. 7.6.46  R45 Register (Offset = 0x2D) [reset = 0xC622]
      47. 7.6.47  R46 Register (Offset = 0x2E) [reset = 0x7F0]
      48. 7.6.48  R47 Register (Offset = 0x2F) [reset = 0x300]
      49. 7.6.49  R48 Register (Offset = 0x30) [reset = 0x3E0]
      50. 7.6.50  R49 Register (Offset = 0x31) [reset = 0x4180]
      51. 7.6.51  R50 Register (Offset = 0x32) [reset = 0x80]
      52. 7.6.52  R51 Register (Offset = 0x33) [reset = 0x80]
      53. 7.6.53  R52 Register (Offset = 0x34) [reset = 0x420]
      54. 7.6.54  R53 Register (Offset = 0x35) [reset = 0x0]
      55. 7.6.55  R54 Register (Offset = 0x36) [reset = 0x0]
      56. 7.6.56  R55 Register (Offset = 0x37) [reset = 0x0]
      57. 7.6.57  R56 Register (Offset = 0x38) [reset = 0x0]
      58. 7.6.58  R57 Register (Offset = 0x39) [reset = 0x0]
      59. 7.6.59  R58 Register (Offset = 0x3A) [reset = 0x8001]
      60. 7.6.60  R59 Register (Offset = 0x3B) [reset = 0x1]
      61. 7.6.61  R60 Register (Offset = 0x3C) [reset = 0x3E8]
      62. 7.6.62  R61 Register (Offset = 0x3D) [reset = 0xA8]
      63. 7.6.63  R62 Register (Offset = 0x3E) [reset = 0xAE]
      64. 7.6.64  R63 Register (Offset = 0x3F) [reset = 0x0]
      65. 7.6.65  R64 Register (Offset = 0x40) [reset = 0x1388]
      66. 7.6.66  R65 Register (Offset = 0x41) [reset = 0x0]
      67. 7.6.67  R66 Register (Offset = 0x42) [reset = 0x140]
      68. 7.6.68  R67 Register (Offset = 0x43) [reset = 0x0]
      69. 7.6.69  R68 Register (Offset = 0x44) [reset = 0x3E8]
      70. 7.6.70  R69 Register (Offset = 0x45) [reset = 0x0]
      71. 7.6.71  R70 Register (Offset = 0x46) [reset = 0xC350]
      72. 7.6.72  R71 Register (Offset = 0x47) [reset = 0x80]
      73. 7.6.73  R72 Register (Offset = 0x48) [reset = 0x1]
      74. 7.6.74  R73 Register (Offset = 0x49) [reset = 0x3F]
      75. 7.6.75  R74 Register (Offset = 0x4A) [reset = 0x0]
      76. 7.6.76  R75 Register (Offset = 0x4B) [reset = 0x800]
      77. 7.6.77  R76 Register (Offset = 0x4C) [reset = 0xC]
      78. 7.6.78  R77 Register (Offset = 0x4D) [reset = 0x0]
      79. 7.6.79  R78 Register (Offset = 0x4E) [reset = 0x64]
      80. 7.6.80  R79 Register (Offset = 0x4F) [reset = 0x0]
      81. 7.6.81  R80 Register (Offset = 0x50) [reset = 0x0]
      82. 7.6.82  R81 Register (Offset = 0x51) [reset = 0x0]
      83. 7.6.83  R82 Register (Offset = 0x52) [reset = 0x0]
      84. 7.6.84  R83 Register (Offset = 0x53) [reset = 0x0]
      85. 7.6.85  R84 Register (Offset = 0x54) [reset = 0x0]
      86. 7.6.86  R85 Register (Offset = 0x55) [reset = 0x0]
      87. 7.6.87  R86 Register (Offset = 0x56) [reset = 0x0]
      88. 7.6.88  R87 Register (Offset = 0x57) [reset = 0x0]
      89. 7.6.89  R88 Register (Offset = 0x58) [reset = 0x0]
      90. 7.6.90  R89 Register (Offset = 0x59) [reset = 0x0]
      91. 7.6.91  R90 Register (Offset = 0x5A) [reset = 0x0]
      92. 7.6.92  R91 Register (Offset = 0x5B) [reset = 0x0]
      93. 7.6.93  R92 Register (Offset = 0x5C) [reset = 0x0]
      94. 7.6.94  R93 Register (Offset = 0x5D) [reset = 0x0]
      95. 7.6.95  R94 Register (Offset = 0x5E) [reset = 0x0]
      96. 7.6.96  R95 Register (Offset = 0x5F) [reset = 0x0]
      97. 7.6.97  R96 Register (Offset = 0x60) [reset = 0x0]
      98. 7.6.98  R97 Register (Offset = 0x61) [reset = 0x0]
      99. 7.6.99  R98 Register (Offset = 0x62) [reset = 0x0]
      100. 7.6.100 R99 Register (Offset = 0x63) [reset = 0x0]
      101. 7.6.101 R100 Register (Offset = 0x64) [reset = 0x0]
      102. 7.6.102 R101 Register (Offset = 0x65) [reset = 0x0]
      103. 7.6.103 R102 Register (Offset = 0x66) [reset = 0x0]
      104. 7.6.104 R103 Register (Offset = 0x67) [reset = 0x0]
      105. 7.6.105 R104 Register (Offset = 0x68) [reset = 0x0]
      106. 7.6.106 R105 Register (Offset = 0x69) [reset = 0x440]
      107. 7.6.107 R106 Register (Offset = 0x6A) [reset = 0x7]
      108. 7.6.108 R107 Register (Offset = 0x6B) [reset = 0x0]
      109. 7.6.109 R108 Register (Offset = 0x6C) [reset = 0x0]
      110. 7.6.110 R109 Register (Offset = 0x6D) [reset = 0x0]
      111. 7.6.111 R110 Register (Offset = 0x6E) [reset = 0x0]
      112. 7.6.112 R111 Register (Offset = 0x6F) [reset = 0x0]
      113. 7.6.113 R112 Register (Offset = 0x70) [reset = 0x0]
      114. 7.6.114 R113 Register (Offset = 0x71) [reset = 0x0]
      115. 7.6.115 R114 Register (Offset = 0x72) [reset = 0x0]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCIN Configuration
      2. 8.1.2 OSCIN Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
        1. 8.1.4.1 Resistor Pullup
        2. 8.1.4.2 Inductor Pullup
        3. 8.1.4.3 Combination Pullup
      5. 8.1.5 RF Output Treatment for the Complimentary Side
        1. 8.1.5.1 Single-Ended Termination of Unused Output
        2. 8.1.5.2 Differential Termination
      6. 8.1.6 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information
  13. 重要声明
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DATA SHEET

LMX2694-EP 具有相位同步功能的 15GHz 宽带 PLLatinum 射频合成器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • VID V62/19616-01XE
  • 39.3MHz 至 15.1GHz 输出频率
  • 在 100KHz 偏频和 15GHz 载波的情况下具有 -110dBc/Hz 的相位噪声
  • 在 8GHz 时，具有 54fs RMS 抖动（100Hz 至 100MHz）
  • 可编程输出功率
  • PLL 主要规格
    • 品质因数：-236dBc/Hz
    • 归一化 1/f 噪声：-129dBc/Hz
    • 相位检测器频率高达 200MHz
  • 跨多个器件实现输出相位同步
  • 支持具有 9ps 分辨率可编程延迟的 SYSREF
  • 3.3V 单电源运行
  • 工作温度范围：-55°C 至 125°C

2 应用

  • 无线电防御
  • 电子战
  • 雷达
  • 有源天线系统 mMIMO (AAS)
  • 宏远程无线电单元
  • 室外回程单元
  • 数据采集
  • 无线通信测试设备

3 说明

LMX2694-EP 器件是一款集成电压控制振荡器 (VCO) 和稳压器的高性能宽带锁相环 (PLL)，在无倍频器的情况，可输出 39.3MHz 至 15.1GHz 范围内的任意频率，从而无需使用 ½ 谐波滤波器。此器件上的 VCO 涵盖了整个倍频区间，因而频率覆盖度可完全低至 39.3MHz。该高性能 PLL 具有 -236dBc/Hz 的品质因数和高相位检测器频率，可实现非常低的带内噪声和集成抖动。

LMX2694-EP 允许设计人员同步多个器件实例的输出。这意味着我们可从任意应用情形下的器件中获得确定性相位，包括采用分数引擎或启用输出分频器的情形。该器件还让设计人员可以生成或重复 SYSREF（符合 JESD204B 标准），以便将该器件用作高速数据转换器的低噪声时钟源。

器件信息(1)
器件型号封装封装尺寸（标称值）
LMX2694-EPVQFN (48)7.00mm × 7.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-5AFF12FC-FCB6-45DB-BF5D-5B71484B10A7-low.gif简化版原理图

4 Revision History

Changes from Revision C (October 2021) to Revision D (March 2022)

  • 将特性 中的 VID V62/19616 可订购型号更改为“VID V62/19616-01XE”Go
  • 将器件信息 表中的 VID V62/19616-01XE 可订购型号移动至数据表末尾的封装信息 表Go

Changes from Revision B (May 2020) to Revision C (October 2021)

  • Removed equivalent division value of 72 in Table 7-8 Go
  • Changed the JESD_DACx values in Table 7-15 Go
  • Changed the R1 register bit name 3 in Table 7-21 from: 1 to: MUXOUT_CTRLGo
  • Changed the OUTA_MUX register description in Table 7-65 Go
  • Changed the OUTB_MUX register description in Table 7-66 Go

Changes from Revision A (December 2019) to Revision B (May 2020)

  • 将最大工作温度更改为 125°CGo
  • Changed maximum TC to 125°C in Recommended Operating ConditionsGo
  • Changed maximum TC to 125°C in Electrical CharacteristicsGo
  • Changed maximum TC to 125°C in Timing RequirementsGo

Changes from Revision * (November 2019) to Revision A (December 2019)

  • 将定制数据表版本更改为产品目录Go

5 Pin Configuration and Functions

Figure 5-1 RTC Package48-Pin VQFNTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
BIASVARAC 41 BP VCO varactor bias. Connect a 10-µF decoupling capacitor to ground.
BIASVCO 3 BP VCO bias. Connect a 10-µF decoupling capacitor to ground. Place close to pin.
BIASVCO2 34 BP VCO bias. Connect a 1-µF decoupling capacitor to ground. Place close to pin.
CE 1 I Chip Enable. High impedance CMOS input. 1.8-V to 3.3-V logic. Active HIGH powers on the device.
CPOUT 14 O Charge pump output. Recommend connecting C1 of loop filter close to this pin.
CS# 28 I SPI latch. High impedance CMOS input. 1.8-V to 3.3-V logic.
GND 2, 4, 32, 40, 42, 47 G VCO ground.
GND 6, 16, 48 G Digital ground.
GND 15 G Charge pump ground.
GND 27, 29 G Buffer ground.
MUXOUT 23 O Multiplexed output. Can output: lock detect, SPI readback and diagnostics.
NC 11, 12, 20, 30, 31, 37, 38, 39 NC Pins may be grounded or left unconnected.
OSCIN_N 9 I Reference input clock (–). High impedance self-biasing pin. Requires AC-coupling capacitor. (0.1 µF recommended)
OSCIN_P 8 I Reference input clock (+). High impedance self-biasing pin. Requires AC-coupling capacitor. (0.1 µF recommended)
REFVCO 44 BP VCO supply reference. Connect a 10-µF decoupling capacitor to ground.
REFVCO2 36 BP VCO supply reference. Connect a 10-µF decoupling capacitor to ground.
REGIN 10 BP Input reference path regulator decoupling. Connect a 1-µF decoupling capacitor to ground. Place close to pin.
REGVCO 46 BP VCO regulator node. Connect a 1-µF decoupling capacitor to ground.
RFOUTA_N 25 O Differential output A (–). Requires connecting 50-Ω resistor pullup to VCC as close as possible to pin.
RFOUTA_P 26 O Differential output A (+). Requires connecting 50-Ω resistor pullup to VCC as close as possible to pin.
RFOUTB_N 21 O Differential output B (–). Requires connecting 50-Ω resistor pullup to VCC as close as possible to pin.
RFOUTB_P 22 O Differential output B (+). Requires connecting 50-Ω resistor pullup to VCC as close as possible to pin.
SCK 18 I SPI clock. High impedance CMOS input. 1.8-V to 3.3-V logic.
SDI 19 I SPI data. High impedance CMOS input. 1.8-V to 3.3-V logic.
SYNC 5 I Phase synchronization input. Has programmable threshold. Connect to ground if not being used.
SYSREFREQ 35 I SYSREF request input for JESD204B support. Connect to ground if not being used.
VCCBUF 24 P Output buffer supply. Connect to 3.3-V and a 0.1-µF decoupling capacitor to ground.
VCCCP 13 P Charge pump supply. Connect to 3.3-V and a 0.1-µF decoupling capacitor to ground.
VCCDIG 7 P Digital supply. Connect to 3.3-V and a 0.1-µF decoupling capacitor to ground.
VCCMASH 17 P Digital supply. Connect to 3.3-V and a 1-µF decoupling capacitor to ground.
VCCVCO 45 P VCO supply. Connect to 3.3-V and a 1-µF decoupling capacitor to ground.
VCCVCO2 33 P VCO supply. Connect to 3.3-V and a 1-µF decoupling capacitor to ground.
VTUNE 43 I VCO tuning voltage input. Connect a 1.5-nF or more capacitor to VCO ground. See Section 8.1.6 for details.
Thermal pad — — Connect the GND pin to the exposed thermal pad for correct operation. Connect the thermal pad to any internal PCB ground plane using multiple vias for good thermal performance.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VCCPower supply voltage–0.33.6V
VINIO input voltageVCC + 0.3V
TJJunction temperature–55150°C
TstgStorage temperature–65150°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±1000V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)±1000
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
TCCase temperature–55125°C
VCCSupply input voltage3.23.33.45V

6.4 Thermal Information

THERMAL METRIC(1)LMX2694-EPUNIT
RTC (VQFN)
48 PINS
RθJAJunction-to-ambient thermal resistance22.4°C/W
RθJC(top)Junction-to-case (top) thermal resistance10.0°C/W
RθJBJunction-to-board thermal resistance6.1°C/W
ΨJTJunction-to-top characterization parameter0.1°C/W
ΨJBJunction-to-board characterization parameter6.0°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance0.7°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

3.2 V ≤ VCC ≤ 3.45 V, –50°C ≤ TC ≤ 125°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
ICC Supply current OUTA_PD = 0; OUTB_PD = 1;
OUTA_MUX = OUTB_MUX = 1;
OUTA_PWR = 31; CPG = 7;
fOSC = fPD = 100 MHz; fVCO = fOUT = 14.5 GHz		 360 mA
Power on reset current RESET = 1 289
Power down current POWERDOWN = 1 6
OUTPUT CHARACTERISTICS
pOUT Single-ended output power(1)(2) 50-Ω resistor pull-up
OUTx_PWR = 31		 fOUT = 8 GHz 2 dBm
fOUT = 15 GHz 0
INPUT SIGNAL PATH
fOSC Reference input frequency OSC_2X = 0 5 1000 MHz
OSC_2X = 1 5 200
VOSC Reference input voltage(3) fOSC ≥ 20 MHz 0.4 2 VPP
10 MHz ≤ fOSC < 20 MHz 0.8 2
5 MHz ≤ fOSC < 10 MHz 1.6 2
PHASE DETECTOR AND CHARGE PUMP
fPD Phase detector frequency(4) MASH_ORDER = 0 0.125 250 MHz
MASH_ORDER > 0 5 200
ICPOUT Charge-pump leakage current CPG = 0 20 nA
Effective charge pump current Sum of the up and down currents 3 15 mA
PNPLL_1/f Normalized PLL 1/f noise fPD = 100 MHz; fVCO = 12 GHz(5) –129 dBc/Hz
PNPLL_FOM Normalized PLL noise floor –236
VCO CHARACTERISTICS
fVCO VCO frequency 7550 15100 MHz
PNVCO VCO phase noise VCO1
fVCO = 8.1 GHz		 100 kHz –106.5 dBc/Hz
1 MHz –128
10 MHz –147.5
100 MHz –154
VCO2
fVCO = 9.3 GHz		 100 kHz –105
1 MHz –126.5
10 MHz –146.5
100 MHz –154
VCO3
fVCO = 10.4 GHz		 100 kHz –103.5
1 MHz –125.5
10 MHz –146
100 MHz –158
VCO4
fVCO = 11.4 GHz		 100 kHz –102.5
1 MHz –124.5
10 MHz –145
100 MHz –160
VCO5
fVCO = 12.5 GHz		 100 kHz –100.5
1 MHz –122.5
10 MHz –143.5
100 MHz –154.5
VCO6
fVCO = 13.6 GHz		 100 kHz –99.5
1 MHz –122
10 MHz –142.5
100 MHz –154
VCO7
fVCO = 14.7 GHz		 100 kHz –98
1 MHz –120.5
10 MHz –141.5
100 MHz –155
tVCOCAL VCO calibration time(6) Switch across the entire frequency band;
fOSC = fPD = 100 MHz;
VCO_SEL = 7		 650 µs
KVCO VCO Gain 8.1 GHz 94 MHz/V
9.3 GHz 106
10.4 GHz 122
11.4 GHz 148
12.5 GHz 185
13.6 GHz 202
14.7 GHz 233
|ΔTCL| Allowable temperature drift VCO not being re-calibrated 125 °C
H2 VCO second harmonic fVCO = 8 GHz; divider disabled –30 dBc
H3 VCO third harmonic fVCO = 8 GHz; divider disabled –25
DIGITAL INTERFACE
VIH High-level input voltage 1.4 V
VIL Low-level input voltage 0.4 V
IIH High-level input current –100 100 µA
IIL Low-level input current –100 100 µA
VOH High-level output voltage Load current = –5 mA MUXOUT pin VCC – 0.6 V
VOL High-level output current Load current = 5 mA 0.6 V
(1) Single ended output power obtained after de-embedding microstrip trace losses and matching with a manual tuner. Unused port terminated to 50-Ω load.
(2) Output power, spurs, and harmonics can vary based on board layout and components.
(3) Single-ended AC coupled sine wave input with complementary side AC coupled to ground with 50-Ω resistor.
(4) For lower VCO frequencies, the N divider minimum value can limit the phase-detector frequency.
(5) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20 x log(fVCO/fPD) + 10 x log(fPD/1 Hz). PLL_flicker (offset) = PLL_1/f + 20 x log(fVCO/1 GHz) - 10 x log(offset/10 kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 x log(10PLL_Flat/10 + 10PLL_flicker/10).
(6) See Section 7.3.7.1 for details.

 
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