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  • ADS7128 小型 8 通道 12 位 ADC，具有 I2C 接口、GPIO 和 CRC

    • ZHCSJS7 May   2019 ADS7128

      ADVANCE INFORMATION for pre-production products; subject to change without notice.  

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  • ADS7128 小型 8 通道 12 位 ADC，具有 I2C 接口、GPIO 和 CRC
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      ADS7128 方框图和 应用
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1      Absolute Maximum Ratings
    2. 7.2      ESD Ratings
    3. 7.3      Recommended Operating Conditions
    4. 7.4      Thermal Information
    5. 7.5      Electrical Characteristics
    6. Table 1. I2C Timing Requirements
    7. Table 2. Timing Requirements
    8. Table 3. I2C Switching Characteristics
    9. 7.6      Switching Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Multiplexer and ADC
      2. 8.3.2  Reference
      3. 8.3.3  ADC Transfer Function
      4. 8.3.4  ADC Offset Calibration
      5. 8.3.5  I2C Address Selector
      6. 8.3.6  Programmable Averaging Filter
      7. 8.3.7  CRC on Data Interface
      8. 8.3.8  General-Purpose I/Os (GPIOs)
      9. 8.3.9  Oscillator and Timing Control
      10. 8.3.10 Output Data Format
      11. 8.3.11 Digital Window Comparator
        1. 8.3.11.1 Interrupts From Digital Inputs
        2. 8.3.11.2 Changing Digital Outputs on Alert and ZCD
          1. 8.3.11.2.1 Changing Digital Outputs on Alerts
            1. 8.3.11.2.1.1 Trigger
            2. 8.3.11.2.1.2 Output Value
          2. 8.3.11.2.2 Changing Digital Outputs Synchronous to the Zero-Crossing Detect
      12. 8.3.12 Root-Mean-Square Module
      13. 8.3.13 Zero-Crossing-Detect Module
      14. 8.3.14 Minimum, Maximum, and Latest Data Registers
      15. 8.3.15 I2C Protocol Features
        1. 8.3.15.1 General Call
        2. 8.3.15.2 General Call With Software Reset
        3. 8.3.15.3 General Call With a Software Write to the Programmable Part of the Slave Address
        4. 8.3.15.4 Configuring the Device for High-Speed I2C Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Power-Up and Reset
      2. 8.4.2 Manual Mode
      3. 8.4.3 Auto-Sequence Mode
      4. 8.4.4 Autonomous Mode
    5. 8.5 Programming
      1. 8.5.1 Reading Registers
        1. 8.5.1.1 Single Register Read
        2. 8.5.1.2 Reading a Continuous Block of Registers
      2. 8.5.2 Writing Registers
        1. 8.5.2.1 Single Register Write
        2. 8.5.2.2 Set Bit
        3. 8.5.2.3 Clear Bit
        4. 8.5.2.4 Writing a Continuous Block of Registers
    6. 8.6 ADS7128 Registers
      1. 8.6.1   SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
        1. Table 15. SYSTEM_STATUS Register Field Descriptions
      2. 8.6.2   GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
        1. Table 16. GENERAL_CFG Register Field Descriptions
      3. 8.6.3   DATA_CFG Register (Address = 0x2) [reset = 0x0]
        1. Table 17. DATA_CFG Register Field Descriptions
      4. 8.6.4   OSR_CFG Register (Address = 0x3) [reset = 0x0]
        1. Table 18. OSR_CFG Register Field Descriptions
      5. 8.6.5   OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
        1. Table 19. OPMODE_CFG Register Field Descriptions
      6. 8.6.6   PIN_CFG Register (Address = 0x5) [reset = 0x0]
        1. Table 20. PIN_CFG Register Field Descriptions
      7. 8.6.7   GPIO_CFG Register (Address = 0x7) [reset = 0x0]
        1. Table 21. GPIO_CFG Register Field Descriptions
      8. 8.6.8   GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
        1. Table 22. GPO_DRIVE_CFG Register Field Descriptions
      9. 8.6.9   GPO_OUTPUT_VALUE Register (Address = 0xB) [reset = 0x0]
        1. Table 23. GPO_OUTPUT_VALUE Register Field Descriptions
      10. 8.6.10  GPI_VALUE Register (Address = 0xD) [reset = 0x0]
        1. Table 24. GPI_VALUE Register Field Descriptions
      11. 8.6.11  ZCD_BLANKING_CFG Register (Address = 0xF) [reset = 0x0]
        1. Table 25. ZCD_BLANKING_CFG Register Field Descriptions
      12. 8.6.12  SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
        1. Table 26. SEQUENCE_CFG Register Field Descriptions
      13. 8.6.13  CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
        1. Table 27. CHANNEL_SEL Register Field Descriptions
      14. 8.6.14  AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
        1. Table 28. AUTO_SEQ_CH_SEL Register Field Descriptions
      15. 8.6.15  ALERT_CH_SEL Register (Address = 0x14) [reset = 0x0]
        1. Table 29. ALERT_CH_SEL Register Field Descriptions
      16. 8.6.16  ALERT_MAP Register (Address = 0x16) [reset = 0x0]
        1. Table 30. ALERT_MAP Register Field Descriptions
      17. 8.6.17  ALERT_PIN_CFG Register (Address = 0x17) [reset = 0x0]
        1. Table 31. ALERT_PIN_CFG Register Field Descriptions
      18. 8.6.18  EVENT_FLAG Register (Address = 0x18) [reset = 0x0]
        1. Table 32. EVENT_FLAG Register Field Descriptions
      19. 8.6.19  EVENT_HIGH_FLAG Register (Address = 0x1A) [reset = 0x0]
        1. Table 33. EVENT_HIGH_FLAG Register Field Descriptions
      20. 8.6.20  EVENT_LOW_FLAG Register (Address = 0x1C) [reset = 0x0]
        1. Table 34. EVENT_LOW_FLAG Register Field Descriptions
      21. 8.6.21  EVENT_RGN Register (Address = 0x1E) [reset = 0x0]
        1. Table 35. EVENT_RGN Register Field Descriptions
      22. 8.6.22  HYSTERESIS_CH0 Register (Address = 0x20) [reset = 0xF0]
        1. Table 36. HYSTERESIS_CH0 Register Field Descriptions
      23. 8.6.23  HIGH_TH_CH0 Register (Address = 0x21) [reset = 0xFF]
        1. Table 37. HIGH_TH_CH0 Register Field Descriptions
      24. 8.6.24  EVENT_COUNT_CH0 Register (Address = 0x22) [reset = 0x0]
        1. Table 38. EVENT_COUNT_CH0 Register Field Descriptions
      25. 8.6.25  LOW_TH_CH0 Register (Address = 0x23) [reset = 0x0]
        1. Table 39. LOW_TH_CH0 Register Field Descriptions
      26. 8.6.26  HYSTERESIS_CH1 Register (Address = 0x24) [reset = 0xF0]
        1. Table 40. HYSTERESIS_CH1 Register Field Descriptions
      27. 8.6.27  HIGH_TH_CH1 Register (Address = 0x25) [reset = 0xFF]
        1. Table 41. HIGH_TH_CH1 Register Field Descriptions
      28. 8.6.28  EVENT_COUNT_CH1 Register (Address = 0x26) [reset = 0x0]
        1. Table 42. EVENT_COUNT_CH1 Register Field Descriptions
      29. 8.6.29  LOW_TH_CH1 Register (Address = 0x27) [reset = 0x0]
        1. Table 43. LOW_TH_CH1 Register Field Descriptions
      30. 8.6.30  HYSTERESIS_CH2 Register (Address = 0x28) [reset = 0xF0]
        1. Table 44. HYSTERESIS_CH2 Register Field Descriptions
      31. 8.6.31  HIGH_TH_CH2 Register (Address = 0x29) [reset = 0xFF]
        1. Table 45. HIGH_TH_CH2 Register Field Descriptions
      32. 8.6.32  EVENT_COUNT_CH2 Register (Address = 0x2A) [reset = 0x0]
        1. Table 46. EVENT_COUNT_CH2 Register Field Descriptions
      33. 8.6.33  LOW_TH_CH2 Register (Address = 0x2B) [reset = 0x0]
        1. Table 47. LOW_TH_CH2 Register Field Descriptions
      34. 8.6.34  HYSTERESIS_CH3 Register (Address = 0x2C) [reset = 0xF0]
        1. Table 48. HYSTERESIS_CH3 Register Field Descriptions
      35. 8.6.35  HIGH_TH_CH3 Register (Address = 0x2D) [reset = 0xFF]
        1. Table 49. HIGH_TH_CH3 Register Field Descriptions
      36. 8.6.36  EVENT_COUNT_CH3 Register (Address = 0x2E) [reset = 0x0]
        1. Table 50. EVENT_COUNT_CH3 Register Field Descriptions
      37. 8.6.37  LOW_TH_CH3 Register (Address = 0x2F) [reset = 0x0]
        1. Table 51. LOW_TH_CH3 Register Field Descriptions
      38. 8.6.38  HYSTERESIS_CH4 Register (Address = 0x30) [reset = 0xF0]
        1. Table 52. HYSTERESIS_CH4 Register Field Descriptions
      39. 8.6.39  HIGH_TH_CH4 Register (Address = 0x31) [reset = 0xFF]
        1. Table 53. HIGH_TH_CH4 Register Field Descriptions
      40. 8.6.40  EVENT_COUNT_CH4 Register (Address = 0x32) [reset = 0x0]
        1. Table 54. EVENT_COUNT_CH4 Register Field Descriptions
      41. 8.6.41  LOW_TH_CH4 Register (Address = 0x33) [reset = 0x0]
        1. Table 55. LOW_TH_CH4 Register Field Descriptions
      42. 8.6.42  HYSTERESIS_CH5 Register (Address = 0x34) [reset = 0xF0]
        1. Table 56. HYSTERESIS_CH5 Register Field Descriptions
      43. 8.6.43  HIGH_TH_CH5 Register (Address = 0x35) [reset = 0xFF]
        1. Table 57. HIGH_TH_CH5 Register Field Descriptions
      44. 8.6.44  EVENT_COUNT_CH5 Register (Address = 0x36) [reset = 0x0]
        1. Table 58. EVENT_COUNT_CH5 Register Field Descriptions
      45. 8.6.45  LOW_TH_CH5 Register (Address = 0x37) [reset = 0x0]
        1. Table 59. LOW_TH_CH5 Register Field Descriptions
      46. 8.6.46  HYSTERESIS_CH6 Register (Address = 0x38) [reset = 0xF0]
        1. Table 60. HYSTERESIS_CH6 Register Field Descriptions
      47. 8.6.47  HIGH_TH_CH6 Register (Address = 0x39) [reset = 0xFF]
        1. Table 61. HIGH_TH_CH6 Register Field Descriptions
      48. 8.6.48  EVENT_COUNT_CH6 Register (Address = 0x3A) [reset = 0x0]
        1. Table 62. EVENT_COUNT_CH6 Register Field Descriptions
      49. 8.6.49  LOW_TH_CH6 Register (Address = 0x3B) [reset = 0x0]
        1. Table 63. LOW_TH_CH6 Register Field Descriptions
      50. 8.6.50  HYSTERESIS_CH7 Register (Address = 0x3C) [reset = 0xF0]
        1. Table 64. HYSTERESIS_CH7 Register Field Descriptions
      51. 8.6.51  HIGH_TH_CH7 Register (Address = 0x3D) [reset = 0xFF]
        1. Table 65. HIGH_TH_CH7 Register Field Descriptions
      52. 8.6.52  EVENT_COUNT_CH7 Register (Address = 0x3E) [reset = 0x0]
        1. Table 66. EVENT_COUNT_CH7 Register Field Descriptions
      53. 8.6.53  LOW_TH_CH7 Register (Address = 0x3F) [reset = 0x0]
        1. Table 67. LOW_TH_CH7 Register Field Descriptions
      54. 8.6.54  MAX_CH0_LSB Register (Address = 0x60) [reset = 0x0]
        1. Table 68. MAX_CH0_LSB Register Field Descriptions
      55. 8.6.55  MAX_CH0_MSB Register (Address = 0x61) [reset = 0x0]
        1. Table 69. MAX_CH0_MSB Register Field Descriptions
      56. 8.6.56  MAX_CH1_LSB Register (Address = 0x62) [reset = 0x0]
        1. Table 70. MAX_CH1_LSB Register Field Descriptions
      57. 8.6.57  MAX_CH1_MSB Register (Address = 0x63) [reset = 0x0]
        1. Table 71. MAX_CH1_MSB Register Field Descriptions
      58. 8.6.58  MAX_CH2_LSB Register (Address = 0x64) [reset = 0x0]
        1. Table 72. MAX_CH2_LSB Register Field Descriptions
      59. 8.6.59  MAX_CH2_MSB Register (Address = 0x65) [reset = 0x0]
        1. Table 73. MAX_CH2_MSB Register Field Descriptions
      60. 8.6.60  MAX_CH3_LSB Register (Address = 0x66) [reset = 0x0]
        1. Table 74. MAX_CH3_LSB Register Field Descriptions
      61. 8.6.61  MAX_CH3_MSB Register (Address = 0x67) [reset = 0x0]
        1. Table 75. MAX_CH3_MSB Register Field Descriptions
      62. 8.6.62  MAX_CH4_LSB Register (Address = 0x68) [reset = 0x0]
        1. Table 76. MAX_CH4_LSB Register Field Descriptions
      63. 8.6.63  MAX_CH4_MSB Register (Address = 0x69) [reset = 0x0]
        1. Table 77. MAX_CH4_MSB Register Field Descriptions
      64. 8.6.64  MAX_CH5_LSB Register (Address = 0x6A) [reset = 0x0]
        1. Table 78. MAX_CH5_LSB Register Field Descriptions
      65. 8.6.65  MAX_CH5_MSB Register (Address = 0x6B) [reset = 0x0]
        1. Table 79. MAX_CH5_MSB Register Field Descriptions
      66. 8.6.66  MAX_CH6_LSB Register (Address = 0x6C) [reset = 0x0]
        1. Table 80. MAX_CH6_LSB Register Field Descriptions
      67. 8.6.67  MAX_CH6_MSB Register (Address = 0x6D) [reset = 0x0]
        1. Table 81. MAX_CH6_MSB Register Field Descriptions
      68. 8.6.68  MAX_CH7_LSB Register (Address = 0x6E) [reset = 0x0]
        1. Table 82. MAX_CH7_LSB Register Field Descriptions
      69. 8.6.69  MAX_CH7_MSB Register (Address = 0x6F) [reset = 0x0]
        1. Table 83. MAX_CH7_MSB Register Field Descriptions
      70. 8.6.70  MIN_CH0_LSB Register (Address = 0x80) [reset = 0xFF]
        1. Table 84. MIN_CH0_LSB Register Field Descriptions
      71. 8.6.71  MIN_CH0_MSB Register (Address = 0x81) [reset = 0xFF]
        1. Table 85. MIN_CH0_MSB Register Field Descriptions
      72. 8.6.72  MIN_CH1_LSB Register (Address = 0x82) [reset = 0xFF]
        1. Table 86. MIN_CH1_LSB Register Field Descriptions
      73. 8.6.73  MIN_CH1_MSB Register (Address = 0x83) [reset = 0xFF]
        1. Table 87. MIN_CH1_MSB Register Field Descriptions
      74. 8.6.74  MIN_CH2_LSB Register (Address = 0x84) [reset = 0xFF]
        1. Table 88. MIN_CH2_LSB Register Field Descriptions
      75. 8.6.75  MIN_CH2_MSB Register (Address = 0x85) [reset = 0xFF]
        1. Table 89. MIN_CH2_MSB Register Field Descriptions
      76. 8.6.76  MIN_CH3_LSB Register (Address = 0x86) [reset = 0xFF]
        1. Table 90. MIN_CH3_LSB Register Field Descriptions
      77. 8.6.77  MIN_CH3_MSB Register (Address = 0x87) [reset = 0xFF]
        1. Table 91. MIN_CH3_MSB Register Field Descriptions
      78. 8.6.78  MIN_CH4_LSB Register (Address = 0x88) [reset = 0xFF]
        1. Table 92. MIN_CH4_LSB Register Field Descriptions
      79. 8.6.79  MIN_CH4_MSB Register (Address = 0x89) [reset = 0xFF]
        1. Table 93. MIN_CH4_MSB Register Field Descriptions
      80. 8.6.80  MIN_CH5_LSB Register (Address = 0x8A) [reset = 0xFF]
        1. Table 94. MIN_CH5_LSB Register Field Descriptions
      81. 8.6.81  MIN_CH5_MSB Register (Address = 0x8B) [reset = 0xFF]
        1. Table 95. MIN_CH5_MSB Register Field Descriptions
      82. 8.6.82  MIN_CH6_LSB Register (Address = 0x8C) [reset = 0xFF]
        1. Table 96. MIN_CH6_LSB Register Field Descriptions
      83. 8.6.83  MIN_CH6_MSB Register (Address = 0x8D) [reset = 0xFF]
        1. Table 97. MIN_CH6_MSB Register Field Descriptions
      84. 8.6.84  MIN_CH7_LSB Register (Address = 0x8E) [reset = 0xFF]
        1. Table 98. MIN_CH7_LSB Register Field Descriptions
      85. 8.6.85  MIN_CH7_MSB Register (Address = 0x8F) [reset = 0xFF]
        1. Table 99. MIN_CH7_MSB Register Field Descriptions
      86. 8.6.86  RECENT_CH0_LSB Register (Address = 0xA0) [reset = 0x0]
        1. Table 100. RECENT_CH0_LSB Register Field Descriptions
      87. 8.6.87  RECENT_CH0_MSB Register (Address = 0xA1) [reset = 0x0]
        1. Table 101. RECENT_CH0_MSB Register Field Descriptions
      88. 8.6.88  RECENT_CH1_LSB Register (Address = 0xA2) [reset = 0x0]
        1. Table 102. RECENT_CH1_LSB Register Field Descriptions
      89. 8.6.89  RECENT_CH1_MSB Register (Address = 0xA3) [reset = 0x0]
        1. Table 103. RECENT_CH1_MSB Register Field Descriptions
      90. 8.6.90  RECENT_CH2_LSB Register (Address = 0xA4) [reset = 0x0]
        1. Table 104. RECENT_CH2_LSB Register Field Descriptions
      91. 8.6.91  RECENT_CH2_MSB Register (Address = 0xA5) [reset = 0x0]
        1. Table 105. RECENT_CH2_MSB Register Field Descriptions
      92. 8.6.92  RECENT_CH3_LSB Register (Address = 0xA6) [reset = 0x0]
        1. Table 106. RECENT_CH3_LSB Register Field Descriptions
      93. 8.6.93  RECENT_CH3_MSB Register (Address = 0xA7) [reset = 0x0]
        1. Table 107. RECENT_CH3_MSB Register Field Descriptions
      94. 8.6.94  RECENT_CH4_LSB Register (Address = 0xA8) [reset = 0x0]
        1. Table 108. RECENT_CH4_LSB Register Field Descriptions
      95. 8.6.95  RECENT_CH4_MSB Register (Address = 0xA9) [reset = 0x0]
        1. Table 109. RECENT_CH4_MSB Register Field Descriptions
      96. 8.6.96  RECENT_CH5_LSB Register (Address = 0xAA) [reset = 0x0]
        1. Table 110. RECENT_CH5_LSB Register Field Descriptions
      97. 8.6.97  RECENT_CH5_MSB Register (Address = 0xAB) [reset = 0x0]
        1. Table 111. RECENT_CH5_MSB Register Field Descriptions
      98. 8.6.98  RECENT_CH6_LSB Register (Address = 0xAC) [reset = 0x0]
        1. Table 112. RECENT_CH6_LSB Register Field Descriptions
      99. 8.6.99  RECENT_CH6_MSB Register (Address = 0xAD) [reset = 0x0]
        1. Table 113. RECENT_CH6_MSB Register Field Descriptions
      100. 8.6.100 RECENT_CH7_LSB Register (Address = 0xAE) [reset = 0x0]
        1. Table 114. RECENT_CH7_LSB Register Field Descriptions
      101. 8.6.101 RECENT_CH7_MSB Register (Address = 0xAF) [reset = 0x0]
        1. Table 115. RECENT_CH7_MSB Register Field Descriptions
      102. 8.6.102 RMS_CFG Register (Address = 0xC0) [reset = 0x0]
        1. Table 116. RMS_CFG Register Field Descriptions
      103. 8.6.103 RMS_LSB Register (Address = 0xC1) [reset = 0x0]
        1. Table 117. RMS_LSB Register Field Descriptions
      104. 8.6.104 RMS_MSB Register (Address = 0xC2) [reset = 0x0]
        1. Table 118. RMS_MSB Register Field Descriptions
      105. 8.6.105 GPO0_TRIG_EVENT_SEL Register (Address = 0xC3) [reset = 0x2]
        1. Table 119. GPO0_TRIG_EVENT_SEL Register Field Descriptions
      106. 8.6.106 GPO1_TRIG_EVENT_SEL Register (Address = 0xC5) [reset = 0x2]
        1. Table 120. GPO1_TRIG_EVENT_SEL Register Field Descriptions
      107. 8.6.107 GPO2_TRIG_EVENT_SEL Register (Address = 0xC7) [reset = 0x2]
        1. Table 121. GPO2_TRIG_EVENT_SEL Register Field Descriptions
      108. 8.6.108 GPO3_TRIG_EVENT_SEL Register (Address = 0xC9) [reset = 0x2]
        1. Table 122. GPO3_TRIG_EVENT_SEL Register Field Descriptions
      109. 8.6.109 GPO4_TRIG_EVENT_SEL Register (Address = 0xCB) [reset = 0x2]
        1. Table 123. GPO4_TRIG_EVENT_SEL Register Field Descriptions
      110. 8.6.110 GPO5_TRIG_EVENT_SEL Register (Address = 0xCD) [reset = 0x2]
        1. Table 124. GPO5_TRIG_EVENT_SEL Register Field Descriptions
      111. 8.6.111 GPO6_TRIG_EVENT_SEL Register (Address = 0xCF) [reset = 0x2]
        1. Table 125. GPO6_TRIG_EVENT_SEL Register Field Descriptions
      112. 8.6.112 GPO7_TRIG_EVENT_SEL Register (Address = 0xD1) [reset = 0x2]
        1. Table 126. GPO7_TRIG_EVENT_SEL Register Field Descriptions
      113. 8.6.113 GPO_VALUE_ZCD_CFG_CH0_CH3 Register (Address = 0xE3) [reset = 0x0]
        1. Table 127. GPO_VALUE_ZCD_CFG_CH0_CH3 Register Field Descriptions
      114. 8.6.114 GPO_VALUE_ZCD_CFG_CH4_CH7 Register (Address = 0xE4) [reset = 0x0]
        1. Table 128. GPO_VALUE_ZCD_CFG_CH4_CH7 Register Field Descriptions
      115. 8.6.115 GPO_ZCD_UPDATE_EN Register (Address = 0xE7) [reset = 0x0]
        1. Table 129. GPO_ZCD_UPDATE_EN Register Field Descriptions
      116. 8.6.116 GPO_TRIGGER_CFG Register (Address = 0xE9) [reset = 0x0]
        1. Table 130. GPO_TRIGGER_CFG Register Field Descriptions
      117. 8.6.117 GPO_VALUE_TRIG Register (Address = 0xEB) [reset = 0x0]
        1. Table 131. GPO_VALUE_TRIG Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Mixed-Channel Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Digital Input
          2. 9.2.1.2.2 Digital Open-Drain Output
        3. 9.2.1.3 Digital Push-Pull Output
  10. 10Power Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

ADS7128 小型 8 通道 12 位 ADC，具有 I2C 接口、GPIO 和 CRC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 小封装尺寸：
    • 3mm × 3mm WQFN
  • 8 通道，可配置为以下任意组合：
    • 最多 8 个模拟输入、数字输入或数字输出
  • 用于 I/O 扩展的 GPIO：
    • 开漏、推挽数字输出
  • 模拟监控：
    • 每个通道的可编程阈值
    • 用于瞬态抑制的事件计数器
  • 宽工作范围：
    • AVDD：2.35V 至 5.5V
    • DVDD：1.65V 至 5.5V
    • 温度范围：–40°C 至 +85°C
  • 用于读取/写入操作的 CRC：
    • 数据读取/写入 CRC
    • 上电配置 CRC
  • I2C 接口：
    • 高达 3.4MHz（高速）
    • 8 个可配置 I2C 地址
  • 可编程均值滤波器
  • 均方根模块：
    • 16 位真正 RMS 输出
    • 可编程 RMS 时间窗口
  • 过零检测模块：
    • 对应于任何模拟输入的 ZCD 输出
    • 内置瞬态抑制和迟滞
    • 数字可调节检测阈值

2 应用

  • 监控功能
  • 便携式仪表
  • 电器
  • 电信基础设施
  • 电源监控

3 说明

ADS7128 是一款易于使用的 8 通道多路复用 12 位逐次逼近寄存器模数转换器 (SAR ADC)。8 个通道可独立配置为模拟输入、数字输入或数字输出。该器件具有一个用于执行 ADC 转换过程的内部振荡器。

ADS7128 通过兼容 I2C 的接口进行通信，可以在自主或单冲转换模式下运行。ADS7128 使用具有可编程高低阈值、迟滞和事件计数器的数字窗口比较器，通过每通道事件触发的中断来实施模拟监控功能。ADS7128 具有用于数据读取/写入操作和上电配置的内置循环冗余校验 (CRC) 功能。ADS7128 具有 一个均方根 (RMS) 模块，可以为任何模拟输入通道计算 16 位真正 RMS 结果。集成式过零检测 (ZCD) 模块可以在接近越过可配置阈值时触发瞬态抑制和迟滞。

器件信息(1)

部件名称 封装 封装尺寸（标称值）
ADS7128 WQFN (16) 3.00mm × 3.00mm
  1. 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

Device Images

ADS7128 方框图和 应用

ADS7128 front_page_diag.gif

4 修订历史记录

日期 修订版本 说明
2019 年 5 月 * 初始发行版。

5 Device Comparison Table

PART NUMBER DESCRIPTION CRC MODULE ZERO-CROSSING-DETECT (ZCD) MODULE ROOT-MEAN-SQUARE (RMS) MODULE
ADS7128 8-channel, 12-bit ADC with I2C interface and GPIOs Yes Yes Yes
ADS7138 Yes No No
ADS7138-Q1 Yes No No

6 Pin Configuration and Functions

RTE Package
16-Pin WQFN
Top View
ADS7128 qfn_package_i2c.gif

Pin Functions

PIN FUNCTION(1) DESCRIPTION
NAME NO.
AIN0/GPIO0 15 AI, DI, DO Channel 0; configurable as either an analog input (default) or a general-purpose input/output (GPIO)
AIN1/GPIO1 16 AI, DI, DO Channel 1; configurable as either an analog input (default) or a GPIO
AIN2/GPIO2 1 AI, DI, DO Channel 2; configurable as either an analog input (default) or a GPIO
AIN3/GPIO3 2 AI, DI, DO Channel 3; configurable as either an analog input (default) or a GPIO
AIN4/GPIO4 3 AI, DI, DO Channel 4; configurable as either an analog input (default) or a GPIO
AIN5/GPIO5 4 AI, DI, DO Channel 5; configurable as either an analog input (default) or a GPIO
AIN6/GPIO6 5 AI, DI, DO Channel 6; configurable as either an analog input (default) or a GPIO
AIN7/GPIO7 6 AI, DI, DO Channel 7; configurable as either an analog input (default) or a GPIO
ADDR 11 AI Input for selecting the device I2C address.
Connect a resistor to this pin from DECAP pin or GND to select one of the eight addresses.
ALERT 12 Digital output Open-drain (default) or push-pull output for the digital comparator
AVDD 7 Supply Analog supply input, also used as the reference voltage to the ADC; connect a 1-µF decoupling capacitor to GND
DECAP 8 Supply Connect a decoupling capacitor to this pin for the internal power supply
DVDD 10 Supply Digital I/O supply voltage; connect a 1-µF decoupling capacitor to GND
GND 9 Supply Ground for the power supply; all analog and digital signals are referred to this pin voltage
SDA 14 DI, DO Serial data input or output for the I2C interface
SCL 13 DI Serial clock for the I2C interface
(1) AI = analog input, DI = digital input, and DO = digital output.

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
DVDD to GND –0.3 5.5 V
AVDD to GND –0.3 5.5 V
AINx/GPOx(3) GND – 0.3 AVDD + 0.3 V
ADDR GND – 0.3 2.1 V
Digital inputs GND – 0.3 5.5 V
Current through any pin except supply pins(2) –10 10 mA
Junction temperature, TJ –40 125 °C
Storage temperature, Tstg –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pin current must be limited to 10mA or less.
(3) AINx/GPIOx refers to pins 1, 2, 3, 4, 5, 6, 15, and 16.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
AVDD Analog supply voltage 2.35 3.3 5.5 V
DVDD Digital supply voltage 1.65 3.3 5.5 V
ANALOG INPUTS
FSR Full-scale input range AINX(1) - GND 0 AVDD V
VIN Absolute input voltage AINX - GND –0.1 AVDD + 0.1 V
TEMPERATURE RANGE
TA Ambient temperature –40 25 85 ℃
(1) AINx refers to AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.

7.4 Thermal Information

THERMAL METRIC(1) ADS7128 UNIT
RTE (WQFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 49.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.4 °C/W
RθJB Junction-to-board thermal resistance 24.7 °C/W
ΨJT Junction-to-top characterization parameter 1.3 °C/W
ΨJB Junction-to-board characterization parameter 24.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 9.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +85°C; typical values at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
CSH Sampling capacitance 12 pF
DC PERFORMANCE
Resolution No missing codes 12 bits
DNL Differential nonlinearity –0.9 ±0.2 0.9 LSB
INL Integral nonlinearity –2 ±0.5 2 LSB
V(OS) Input offset error Post offset calibration –2 ±0.3 2 LSB
Input offset thermal drift Post offset calibration ±5 ppm/°C
GE Gain error –0.1 ±0.05 0.1 %FSR
Gain error thermal drift ±5 ppm/°C
AC PERFORMANCE
SINAD Signal-to-noise + distortion ratio AVDD = 5 V, fIN = 2 kHz 68.5 71.5 dB
AVDD = 3 V, fIN = 2 kHz 67.5 70.5
SNR Signal-to-noise ratio AVDD = 5 V, fIN = 2 kHz 69 72 dB
AVDD = 3 V, fIN = 2 kHz 68 71
Crosstalk 100-kHz signal applied on any OFF channel and measured on the ON channel –100 dB
DECAP Pin
Decoupling capacitor on DECAP pin 0.22 1 µF
DIGITAL INPUT/OUTPUT (SCL, SDA)
VIH Input high logic level All I2C modes 0.7 x DVDD 5.5 V
VIL Input low logic level All I2C modes –0.3 0.3 x DVDD V
VOL Output low logic level Sink current = 2 mA, DVDD > 2 V 0 0.4 V
Sink current = 2 mA, DVDD ≤ 2 V 0 0.2 x DVDD
IOL Low-level output current (sink) VOL = 0.4 V, standard and fast mode 3 mA
VOL = 0.6 V, fast mode 6
VOL = 0.4 V, fast mode plus 20
GPIOs
VIH Input high logic level 0.7 x AVDD AVDD + 0.3 V
VIL Input low logic level –0.3 0.3 x AVDD V
Input leakge current GPIO configured as input 10 100 nA
VOH Output high logic level GPO_DRIVE_CFG = push-pull, ISOURCE = 2 mA 0.8 x AVDD AVDD V
VOL Output low logic level ISINK = 2 mA 0 0.2 x AVDD V
IOH Output high source current VOH > 0.7 x AVDD 5 mA
IOL Output low sink current VOL < 0.3 x AVDD 5 mA
DIGITAL OUTPUT (ALERT)
VOH Output high logic level GPO_DRIVE_CFG = push-pull, ISOURCE = 2 mA 0.8 x DVDD DVDD V
VOL Output low logic level ISINK = 2 mA 0 0.2 x DVDD V
IOH Output high sink current VOH > 0.7 x DVDD 5 mA
IOL Output low sink current VOL < 0.3 x DVDD 5 mA
POWER SUPPLY CURRENTS
IAVDD Analog supply current I2C high-speed mode, AVDD = 5 V 260 430 µA
I2C fast mode plus, AVDD = 5 V 83 140
I2C fast mode, AVDD = 5 V 35 57
I2C standard mode, AVDD = 5 V 10 20
No conversion, AVDD = 5 V 5 15

Table 1. I2C Timing Requirements

MODE UNIT
FAST MODE HIGH-SPEED MODE
MIN MAX MIN MAX
fSCL SCL clock frequency(1) 1 3.4 MHz
tSUSTA START condition setup time for repeated start 260 160 ns
tHDSTA Start condition hold time 260 160 ns
tLOW Clock low period 500 160 ns
tHIGH Clock high period 260 60 ns
tSUDAT Data in setup time 50 10 ns
tHDDAT Data in hold time 0 0 ns
tR SCL rise time 120 80 ns
tF SCL fall time 120 80 ns
tSUSTO STOP condition hold time 260 60 ns
tBUF Bus free time before new transmission 500 300 ns
(1) Bus load (CB) consideration; CB ≤ 400 pF for fSCL ≤ 1 MHz; CB < 100 pF for fSCL = 3.4 MHz.

Table 2. Timing Requirements

at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +85°C; typical values at TA = 25°C.
MIN MAX UNIT
tACQ Acquisition time 300 ns

Table 3. I2C Switching Characteristics

MODE UNIT
FAST MODE HIGH-SPEED MODE
MIN MAX MIN MAX
tVDDATA SCL low to SDA data out valid 450 200 ns
tVDACK SCL low to SDA acknowledge time 450 200 ns
tSTRETCH Clock stretch time in one-shot conversion mode; during ADC conversion 1200 950 ns
tSP Noise supression time constant on SDA and SCL 50 10 ns

7.6 Switching Characteristics

at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +85°C; typical values at TA = 25°C.
PARAMETER TEST CONDITIONS MIN MAX UNIT
CONVERSION CYCLE
tCONV ADC conversion time Manual and auto sequence modes tSTRETCH ns
Autonomous mode 550 ns
RESET AND ALERT
tPU Power-up time for device AVDD ≥ 2.35 V 5 ms
tRST Delay time; RST bit = 1b to device reset complete(1) 5 ms
tALERT_HI ALERT high period ALERT_LOGIC[1:0] = 1x 85 105 ns
tALERT_LO ALERT low period ALERT_LOGIC[1:0] = 1x 85 105 ns
(1) RST bit is automatically reset to 0b after tRST.
ADS7128 i2c_timing.gif

NOTE:

S = start, Sr = repeated start, and P = stop.
Figure 1. I2C Timing Diagram

8 Detailed Description

8.1 Overview

The ADS7128 is a small, eight-channel, multiplexed, 12-bit, analog-to-digital converter (ADC) with an I2C-compatible serial interface. The eight channels of the ADS7128 can be individually configured as either analog inputs, digital inputs, or digital outputs. The device includes a digital comparator with a dedicated alert pin that can be used to interrupt the host when a programmed high or low threshold is crossed on any input channel. The device uses an internal oscillator for conversion. The ADC can be used in the manual mode for reading ADC data over the I2C interface or in autonomous mode for monitoring the analog inputs without an active I2C interface.

The device features a programmable averaging filter that outputs a 16-bit result for enhanced resolution. The root-mean-square (RMS) module computes a 16-bit true RMS result of any analog input channel over a configurable time window. The zero-crossing-detect (ZCD) module can be used to generate a digital output corresponding to the programmable threshold crossings of any analog input channel.

The I2C serial interface supports standard-mode, fast-mode, fast-mode plus, and high-speed mode. The device also features an 8-bit cyclic redundancy check (CRC) for the serial communication interface.

8.2 Functional Block Diagram

ADS7128 block_diagram.gif

8.3 Feature Description

 
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