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  • 具有 PGA 和电压基准的 ADS125H02 ±20V 输入、双通道、40kSPS、24 位 Δ-Σ ADC

    • ZHCSIZ6C October   2018  – June 2019 ADS125H02

      PRODUCTION DATA.  

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  • 具有 PGA 和电压基准的 ADS125H02 ±20V 输入、双通道、40kSPS、24 位 Δ-Σ ADC
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     功能方框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Range
      2. 9.3.2 Analog Inputs
        1. 9.3.2.1 ESD Diodes
        2. 9.3.2.2 Input Multiplexer
          1. 9.3.2.2.1 Analog Inputs (AIN0, AIN1, AINCOM)
          2. 9.3.2.2.2 High-Voltage Power Supply Readback
          3. 9.3.2.2.3 Internal VCOM Connection (Default)
          4. 9.3.2.2.4 Temperature Sensor
      3. 9.3.3 Programmable Gain Amplifier (PGA)
        1. 9.3.3.1 PGA Operating Range
        2. 9.3.3.2 PGA Monitor
      4. 9.3.4 Reference Voltage
        1. 9.3.4.1 Internal Reference
        2. 9.3.4.2 External Reference
        3. 9.3.4.3 AVDD Power-Supply Reference
        4. 9.3.4.4 Reference Monitor
      5. 9.3.5 Current Sources (IDAC1 and IDAC2)
      6. 9.3.6 General-Purpose Inputs and Outputs (GPIOs)
      7. 9.3.7 ADC Modulator
      8. 9.3.8 Digital Filter
        1. 9.3.8.1 Sinc Filter Mode
          1. 9.3.8.1.1 Sinc Filter Frequency Response
        2. 9.3.8.2 FIR Filter
        3. 9.3.8.3 50-Hz and 60-Hz Normal Mode Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Control
        1. 9.4.1.1 Continuous-Conversion Mode
        2. 9.4.1.2 Pulse-Conversion Mode
        3. 9.4.1.3 Conversion Latency
        4. 9.4.1.4 Start-Conversion Delay
      2. 9.4.2 Auto-Zero Mode
      3. 9.4.3 Clock Mode
      4. 9.4.4 Reset
        1. 9.4.4.1 Power-On Reset
        2. 9.4.4.2 Reset by Pin
        3. 9.4.4.3 Reset by Command
      5. 9.4.5 Calibration
        1. 9.4.5.1 Offset and Full-Scale Calibration
          1. 9.4.5.1.1 Offset Calibration Registers
          2. 9.4.5.1.2 Full-Scale Calibration Registers
        2. 9.4.5.2 Offset Calibration (OFSCAL)
        3. 9.4.5.3 Full-Scale Calibration (GANCAL)
        4. 9.4.5.4 Calibration Command Procedure
        5. 9.4.5.5 User Calibration Procedure
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip-Select Pins (CS1 and CS2)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
      2. 9.5.2 Data Ready (DRDY)
        1. 9.5.2.1 DRDY in Continuous-Conversion Mode
        2. 9.5.2.2 DRDY in Pulse-Conversion Mode
        3. 9.5.2.3 Data Ready by Software Polling
      3. 9.5.3 Conversion Data
        1. 9.5.3.1 Status Byte (STATUS0)
        2. 9.5.3.2 Conversion Data Format
      4. 9.5.4 Cyclic Redundancy Check (CRC)
      5. 9.5.5 Commands
        1. 9.5.5.1  General Command Format
        2. 9.5.5.2  NOP Command
        3. 9.5.5.3  RESET Command
        4. 9.5.5.4  START Command
        5. 9.5.5.5  STOP Command
        6. 9.5.5.6  RDATA Command
        7. 9.5.5.7  OFSCAL Command
        8. 9.5.5.8  GANCAL Command
        9. 9.5.5.9  RREG Command
        10. 9.5.5.10 WREG Command
        11. 9.5.5.11 LOCK Command
        12. 9.5.5.12 UNLOCK Command
    6. 9.6 Register Map
      1. 9.6.1  Device Identification (ID) Register (address = 00h) [reset = 6xh]
        1. Table 30. ID Register Field Descriptions
      2. 9.6.2  Main Status (STATUS0) Register (address = 01h) [reset = 01h]
        1. Table 31. STATUS0 Register Field Descriptions
      3. 9.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
        1. Table 32. MODE0 Register Field Descriptions
      4. 9.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
        1. Table 33. MODE1 Register Field Descriptions
      5. 9.6.5  Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
        1. Table 34. MODE2 Register Field Descriptions
      6. 9.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
        1. Table 35. MODE3 Register Field Descriptions
      7. 9.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
        1. Table 36. REF Register Field Descriptions
      8. 9.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
        1. Table 37. OFCAL0, OFCAL1, OFCAL2 Registers Field Description
      9. 9.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
        1. Table 38. FSCAL0, FSCAL1, FSCAL2 Registers Field Description
      10. 9.6.10 Current Source Multiplexer (I_MUX) Register (address = 0Dh) [reset = FFh]
        1. Table 39. I_MUX Register Field Descriptions
      11. 9.6.11 Current Source Magnitude (I_MAG) Register (address = 0Eh) [reset = 00h]
        1. Table 40. I_MAG Register Field Descriptions
      12. 9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
        1. Table 41. RESERVED Register Field Descriptions
      13. 9.6.13 MODE4 (MODE4) Register (address = 10h) [reset = 50h]
        1. Table 42. MODE4 Register Field Descriptions
      14. 9.6.14 PGA Alarm (STATUS1) Register (address = 11h) [reset = xxh]
        1. Table 43. STATUS1 Register Field Descriptions
      15. 9.6.15 Status 2 (STATUS2) Register (address = 12h) [reset = 0xh]
        1. Table 44. STATUS2 Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Range
      2. 10.1.2 Input Overload
        1. 10.1.2.1 Input Signal Rate of Change (dV/dt)
      3. 10.1.3 Unused Inputs and Outputs
    2. 10.2 Typical Applications
      1. 10.2.1 ±10-V Analog Input Module
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Thermocouple Input With High Common-Mode Voltage
    3. 10.3 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
    4. 11.4 5-V to ±15-V DC-DC Converter
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息
  15. 重要声明
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DATA SHEET

具有 PGA 和电压基准的 ADS125H02 ±20V 输入、双通道、40kSPS、24 位 Δ-Σ ADC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • ±20V 输入、24 位 Δ-Σ ADC
  • 可编程数据速率：2.5SPS 至 40000SPS
  • 高压高阻抗 PGA：
    • 差分输入范围：高达 ±20V
    • 可编程增益：0.125 至 128
    • 共模输入电压：高达 ±15.5V
    • 输入阻抗：1GΩ（最小值）
  • 高性能 ADC：
    • 输入噪声：45nVRMS (20SPS)
    • CMRR：105dB
    • 在 50Hz、60Hz 下的常规模式抑制：95dB
    • 温漂：5nV/°C
    • 增益漂移：1ppm/°C
    • 积分非线性 (INL)：2ppm
  • 集成 特性 和诊断功能：
    • 2.5V 基准：3ppm/°C 漂移
    • 时钟振荡器：2.5% 误差（最大值）
    • 激励电流源
    • GPIO 可驱动外部多路复用器
    • 信号和基准电压监控器
    • 循环冗余校验 (CRC)
  • 电源：
    • AVDD：4.75V 至 5.25V
    • DVDD：2.7V 至 5.25V
    • HVDD：±5V 至 ±18V
  • 工作温度：–40°C 至 +125°C
  • 5mm × 5mm VQFN 封装

2 应用

  • PLC 模拟输入模块：
    • 电压（例如 ±10V 或 0V 至 5V）
    • 电流（例如 4mA 至 20mA，具有分流器）
    • 温度（例如 RTD、热电偶）
  • 测试和测量：
    • 高共模电压输入
    • 电池测试
    • 高侧电流测量

3 说明

ADS125H02 是一款 ±20V 输入、24 位、Δ-Σ 模数转换器 (ADC)。该 ADC 配备 低噪声可编程增益放大器 (PGA)、内部基准电压、时钟振荡器和信号或基准电压超范围监控器。

与分立的解决方案相比，该产品将一个宽输入电压范围、±18V PGA 和 ADC 集成到单个封装中，可将电路板面积减小最多 50%。

具有 0.125 至 128 的可编程增益（相当于 ±20V 至 ±20mV 的等效输入范围），因而无需外部衰减器或外部增益级。1GΩ 的最低输入阻抗可减小由传感器负载导致的误差。而且，由于具备低噪声和低漂移性能，因而能直接连接桥、电阻式温度检测器 (RTD) 和热电偶传感器。

数字滤波器可减弱数据速率 ≤ 50SPS 或 60SPS 时的 50Hz 和 60Hz 线路周期噪声，以减小测量误差。滤波器还可提供无延迟转换数据，从而在通道定序期间实现高数据吞吐量。

ADS125H02 采用 5mm × 5mm VQFN 封装，额定工作温度范围为 –40°C 至 +125°C。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
ADS125H02 VQFN (32) 5.00mm × 5.00mm
  1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

功能方框图

ADS125H02 ai_fbd_d_sbas790.gif

4 修订历史记录

Changes from B Revision (April 2019) to C Revision

  • Deleted 从文档中删除了 ADS125H01Go
  • Changed Device Comparison TableGo
  • Added Effective resolution parameter to Electrical Characteristics tableGo
  • Added Offset Voltage Long-Term Drift curves to Typical CharacteristicsGo
  • Added Gain Long-Term Drift curves to Typical CharacteristicsGo
  • Added Internal Reference Voltage Long-Term Drift curve to Typical CharacteristicsGo
  • Added Oscillator Frequency Long-Term Drift curve to Typical CharacteristicsGo
  • Changed Noise Performance sectionGo
  • Added effective resolution and noise-free resolution data in Noise PerformanceGo
  • Changed sinc1, sinc3, sinc4, and sinc5 values and footnote in Conversion Latency Time tableGo
  • Changed start-conversion delay value from 0 µs to 50 µs in the Start-Conversion Delay sectionGo
  • Changed sinc mode values in Calibration Time tableGo
  • Changed address 00h default value from xxh to 6xh in Register Map Summary tableGo
  • Changed reset value from xxh to 6xh in Device Identification (ID) RegisterGo

Changes from A Revision (January 2019) to B Revision

  • Changed 将 ADS125H02 的状态从“预告信息”更改成了“生产数据”Go

5 Device Comparison Table

PART NUMBER SINGLE-ENDED, DIFFERENTIAL CHANNELS INTERNAL REFERENCE GPIOs SENSOR CURRENT SOURCES TEMPERATURE SENSOR
ADS125H01 1, 1 No 0 0 No
ADS125H02 2, 1 Yes 4 2 Yes

6 Pin Configuration and Functions

RHB Package: ADS125H02
32-Pin VQFN
Top View

Pin Functions

NO. NAME I/O DESCRIPTION
1 REFP0 Analog input Reference input 0 positive
2 CAPP Analog output PGA output P; connect a 1-nF C0G dielectric capacitor from CAPP to CAPN
3 CAPN Analog output PGA output N; connect a 1-nF C0G dielectric capacitor from CAPP to CAPN
4 AVDD Analog Low-voltage analog power supply (5 V)
5 AGND Analog Analog ground; connect to the ADC ground plane
6 REFOUT Analog output 2.5-V reference output; connect a 10-µF capacitor to AGND
7 RESET Digital input Reset; active low
8 START Digital input Conversion start, active high
9 CS2 Digital input Serial interface chip select 2 to select the PGA for communication
10 CS1 Digital input Serial interface chip select 1 to select the ADC for communication
11 SCLK Digital input Serial interface shift clock
12 DIN Digital input Serial interface data input
13 DRDY Digital output Data-ready indicator; active low
14 DOUT/DRDY Digital output Serial interface data output and data-ready indicator (active low)
15 BYPASS Analog output 2-V subregulator output; connect a 1-µF capacitor to DGND
16 DGND Digital Digital ground; connect to the ADC ground plane
17 DVDD Digital Digital power supply (3 V to 5 V)
18 CLKIN Digital input External clock input. Connect to DGND for internal oscillator operation.
19 HV_AVSS Analog High-voltage negative analog power supply
20 HV_AVDD Analog High-voltage positive analog power supply
21, 22 NC — No connection; electrically float or tie to AGND
23 IDAC2 Analog output Current source 2 output
24 IDAC1 Analog output Current source 1 output
25 AINCOM Analog input Analog input common (single-ended common input)
26 AIN0 Analog input Analog input 0
27 AIN1 Analog input Analog input 1
28 GPIO3 Digital
input/output		 General-purpose input/output 3
29 GPIO2 Digital
input/output		 General-purpose input/output 2
30 REFN1/GPIO1 Analog, digital
input/output		 Reference input 1 negative and general-purpose input/output 1
31 REFP1/GPIO0 Analog, digital
input/output		 Reference input 1 positive and general-purpose input/output 0
32 REFN0 Analog input Reference input 0 negative
Thermal pad — Exposed thermal pad; connect to DGND; see the recommended PCB land pattern at the end of the document.

7 Specifications

7.1 Absolute Maximum Ratings

see (1)
MIN MAX UNIT
Power-supply voltage HV_AVDD to HV_AVSS –0.3 38 V
HV_AVSS to AGND –19 0.3
AVDD to AGND –0.3 6
DVDD to DGND –0.3 6
AGND to DGND –0.1 0.1
Analog input voltage AIN0, AIN1, AINCOM HV_AVSS – 0.3 HV_AVDD + 0.3 V
GPIO[3:0], REFP[1:0], REFN[1:0], IDAC[2:1] AGND – 0.3 AVDD + 0.3
Digital input voltage CS1, CS2, SCLK, DIN, START, RESET, CLKIN, DRDY, DOUT/DRDY DGND – 0.3 DVDD + 0.3 V
Input current Continuous (2) –10 10 mA
Temperature Junction, TJ 150 °C
Storage, Tstg –60 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input and output pins are diode-clamped to the internal power supplies. Limit the input current to 10 mA in the event the analog input voltage exceeds HV_AVDD + 0.3 V or HV_AVSS – 0.3 V, or if the reference input, GPIO, or IDAC voltage exceeds AVDD + 0.3 V or AGND – 0.3 V, or if the digital input voltage exceeds DVDD + 0.3 V or DGND – 0.3 V.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

 
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