ADS125H02 是一款 ±20V 输入、24 位、Δ-Σ 模数转换器 (ADC)。该 ADC 配备 低噪声可编程增益放大器 (PGA)、内部基准电压、时钟振荡器和信号或基准电压超范围监控器。
与分立的解决方案相比,该产品将一个宽输入电压范围、±18V PGA 和 ADC 集成到单个封装中,可将电路板面积减小最多 50%。
具有 0.125 至 128 的可编程增益(相当于 ±20V 至 ±20mV 的等效输入范围),因而无需外部衰减器或外部增益级。1GΩ 的最低输入阻抗可减小由传感器负载导致的误差。而且,由于具备低噪声和低漂移性能,因而能直接连接桥、电阻式温度检测器 (RTD) 和热电偶传感器。
数字滤波器可减弱数据速率 ≤ 50SPS 或 60SPS 时的 50Hz 和 60Hz 线路周期噪声,以减小测量误差。滤波器还可提供无延迟转换数据,从而在通道定序期间实现高数据吞吐量。
ADS125H02 采用 5mm × 5mm VQFN 封装,额定工作温度范围为 –40°C 至 +125°C。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
ADS125H02 | VQFN (32) | 5.00mm × 5.00mm |
Changes from B Revision (April 2019) to C Revision
Changes from A Revision (January 2019) to B Revision
NO. | NAME | I/O | DESCRIPTION |
---|---|---|---|
1 | REFP0 | Analog input | Reference input 0 positive |
2 | CAPP | Analog output | PGA output P; connect a 1-nF C0G dielectric capacitor from CAPP to CAPN |
3 | CAPN | Analog output | PGA output N; connect a 1-nF C0G dielectric capacitor from CAPP to CAPN |
4 | AVDD | Analog | Low-voltage analog power supply (5 V) |
5 | AGND | Analog | Analog ground; connect to the ADC ground plane |
6 | REFOUT | Analog output | 2.5-V reference output; connect a 10-µF capacitor to AGND |
7 | RESET | Digital input | Reset; active low |
8 | START | Digital input | Conversion start, active high |
9 | CS2 | Digital input | Serial interface chip select 2 to select the PGA for communication |
10 | CS1 | Digital input | Serial interface chip select 1 to select the ADC for communication |
11 | SCLK | Digital input | Serial interface shift clock |
12 | DIN | Digital input | Serial interface data input |
13 | DRDY | Digital output | Data-ready indicator; active low |
14 | DOUT/DRDY | Digital output | Serial interface data output and data-ready indicator (active low) |
15 | BYPASS | Analog output | 2-V subregulator output; connect a 1-µF capacitor to DGND |
16 | DGND | Digital | Digital ground; connect to the ADC ground plane |
17 | DVDD | Digital | Digital power supply (3 V to 5 V) |
18 | CLKIN | Digital input | External clock input. Connect to DGND for internal oscillator operation. |
19 | HV_AVSS | Analog | High-voltage negative analog power supply |
20 | HV_AVDD | Analog | High-voltage positive analog power supply |
21, 22 | NC | — | No connection; electrically float or tie to AGND |
23 | IDAC2 | Analog output | Current source 2 output |
24 | IDAC1 | Analog output | Current source 1 output |
25 | AINCOM | Analog input | Analog input common (single-ended common input) |
26 | AIN0 | Analog input | Analog input 0 |
27 | AIN1 | Analog input | Analog input 1 |
28 | GPIO3 | Digital
input/output |
General-purpose input/output 3 |
29 | GPIO2 | Digital
input/output |
General-purpose input/output 2 |
30 | REFN1/GPIO1 | Analog, digital
input/output |
Reference input 1 negative and general-purpose input/output 1 |
31 | REFP1/GPIO0 | Analog, digital
input/output |
Reference input 1 positive and general-purpose input/output 0 |
32 | REFN0 | Analog input | Reference input 0 negative |
Thermal pad | — | Exposed thermal pad; connect to DGND; see the recommended PCB land pattern at the end of the document. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power-supply voltage | HV_AVDD to HV_AVSS | –0.3 | 38 | V |
HV_AVSS to AGND | –19 | 0.3 | ||
AVDD to AGND | –0.3 | 6 | ||
DVDD to DGND | –0.3 | 6 | ||
AGND to DGND | –0.1 | 0.1 | ||
Analog input voltage | AIN0, AIN1, AINCOM | HV_AVSS – 0.3 | HV_AVDD + 0.3 | V |
GPIO[3:0], REFP[1:0], REFN[1:0], IDAC[2:1] | AGND – 0.3 | AVDD + 0.3 | ||
Digital input voltage | CS1, CS2, SCLK, DIN, START, RESET, CLKIN, DRDY, DOUT/DRDY | DGND – 0.3 | DVDD + 0.3 | V |
Input current | Continuous (2) | –10 | 10 | mA |
Temperature | Junction, TJ | 150 | °C | |
Storage, Tstg | –60 | 150 |