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  • ADS126x精密 5 通道和 10 通道 40kSPS 24 位 Δ-Σ ADC

    • ZHCSHW1C March   2018  – January 2019 ADS1260 , ADS1261

      PRODUCTION DATA.  

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  • ADS126x精密 5 通道和 10 通道 40kSPS 24 位 Δ-Σ ADC
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
        1. 9.3.1.1 ESD Diodes
        2. 9.3.1.2 Input Multiplexer
        3. 9.3.1.3 Temperature Sensor
        4. 9.3.1.4 Power-Supply Readback
        5. 9.3.1.5 Inputs Open
        6. 9.3.1.6 Internal VCOM Connection
        7. 9.3.1.7 Alternate Functions
      2. 9.3.2  PGA
        1. 9.3.2.1 PGA Bypass Mode
        2. 9.3.2.2 PGA Voltage Monitor
      3. 9.3.3  Reference Voltage
        1. 9.3.3.1 Internal Reference
        2. 9.3.3.2 External Reference
        3. 9.3.3.3 AVDD - AVSS Reference (Default)
        4. 9.3.3.4 Reference Monitor
      4. 9.3.4  Level-Shift Voltage (VBIAS)
      5. 9.3.5  Burn-Out Current Sources
      6. 9.3.6  Sensor-Excitation Current Sources (IDAC1 and IDAC2)
      7. 9.3.7  General-Purpose Input/Outputs (GPIOs)
      8. 9.3.8  Oversampling
      9. 9.3.9  Modulator
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Sinc Filter
          1. 9.3.10.1.1 Sinc Filter Frequency Response
        2. 9.3.10.2 FIR Filter
          1. 9.3.10.2.1 FIR Filter Frequency Response
        3. 9.3.10.3 Filter Bandwidth
        4. 9.3.10.4 50-Hz and 60-Hz Normal Mode Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Control
        1. 9.4.1.1 Continuous-Conversion Mode
        2. 9.4.1.2 Pulse-Conversion Mode
        3. 9.4.1.3 Conversion Latency
        4. 9.4.1.4 Start-Conversion Delay
      2. 9.4.2 Chop Mode
      3. 9.4.3 AC-Excitation Mode
      4. 9.4.4 ADC Clock Mode
      5. 9.4.5 Power-Down Mode
        1. 9.4.5.1 Hardware Power-Down
        2. 9.4.5.2 Software Power-Down
      6. 9.4.6 Reset
        1. 9.4.6.1 Power-on Reset
        2. 9.4.6.2 Reset by Pin
        3. 9.4.6.3 Reset by Command
      7. 9.4.7 Calibration
        1. 9.4.7.1 Offset and Full-Scale Calibration
          1. 9.4.7.1.1 Offset Calibration Registers
          2. 9.4.7.1.2 Full-Scale Calibration Registers
        2. 9.4.7.2 Offset Self-Calibration (SFOCAL)
        3. 9.4.7.3 Offset System-Calibration (SYOCAL)
        4. 9.4.7.4 Full-Scale Calibration (GANCAL)
        5. 9.4.7.5 Calibration Command Procedure
        6. 9.4.7.6 User Calibration Procedure
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
        5. 9.5.1.5 Serial Interface Auto-Reset
      2. 9.5.2 Data Ready (DRDY)
        1. 9.5.2.1 DRDY in Continuous-Conversion Mode
        2. 9.5.2.2 DRDY in Pulse-Conversion Mode
        3. 9.5.2.3 Data Ready by Software Polling
      3. 9.5.3 Conversion Data
        1. 9.5.3.1 Status byte (STATUS)
        2. 9.5.3.2 Conversion Data Format
      4. 9.5.4 CRC
      5. 9.5.5 Commands
        1. 9.5.5.1  NOP Command
        2. 9.5.5.2  RESET Command
        3. 9.5.5.3  START Command
        4. 9.5.5.4  STOP Command
        5. 9.5.5.5  RDATA Command
        6. 9.5.5.6  SYOCAL Command
        7. 9.5.5.7  GANCAL Command
        8. 9.5.5.8  SFOCAL Command
        9. 9.5.5.9  RREG Command
        10. 9.5.5.10 WREG Command
        11. 9.5.5.11 LOCK Command
        12. 9.5.5.12 UNLOCK Command
    6. 9.6 Register Map
      1. 9.6.1  Device Identification (ID) Register (address = 00h) [reset = xxh]
        1. Table 30. ID Register Field Descriptions
      2. 9.6.2  Device Status (STATUS) Register (address = 01h) [reset = 01h]
        1. Table 31. STATUS Register Field Descriptions
      3. 9.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
        1. Table 32. MODE0 Register Field Descriptions
      4. 9.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
        1. Table 33. MODE1 Register Field Descriptions
      5. 9.6.5  Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
        1. Table 34. MODE2 Register Field Descriptions
      6. 9.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
        1. Table 35. MODE3 Register Field Descriptions
      7. 9.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
        1. Table 36. REF Register Field Descriptions
      8. 9.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
        1. Table 37. OFCAL0, OFCAL1, OFCAL2 Registers Field Description
      9. 9.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
        1. Table 38. FSCAL0, FSCAL1, FSCAL2 Registers Field Description
      10. 9.6.10 IDAC Multiplexer (IMUX) Register (address = 0Dh) [reset = FFh]
        1. Table 39. IMUX Register Field Descriptions
      11. 9.6.11 IDAC Magnitude (IMAG) Register (address = 0Eh) [reset = 00h]
        1. Table 40. IMAG Register Field Descriptions
      12. 9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
        1. Table 41. RESERVED Register Field Descriptions
      13. 9.6.13 PGA Configuration (PGA) Register (address = 10h) [reset = 00h]
        1. Table 42. PGA Register Field Descriptions
      14. 9.6.14 Input Multiplexer (INPMUX) Register (address = 11h) [reset = FFh]
        1. Table 43. INPMUX Register Field Descriptions
      15. 9.6.15 Input Bias (INPBIAS) Register (address = 12h) [reset = 00h]
        1. Table 44. INPBIAS Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Range
      2. 10.1.2 Input Overload
      3. 10.1.3 Burn-Out Current Source
      4. 10.1.4 Unused Inputs and Outputs
      5. 10.1.5 AC-Excitation
      6. 10.1.6 Serial Interface and Digital Connections
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14机械、封装和可订购信息
  15. 重要声明
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DATA SHEET

ADS126x精密 5 通道和 10 通道 40kSPS 24 位 Δ-Σ ADC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 24 位高精度 ADC
    • 温漂：1nV/°C
    • 增益漂移：0.5ppm/°C
    • 噪声：30nVRMS（20SPS，增益 = 128）
    • 线性度：2ppm
  • CMOS PGA 增益：1 至 128
  • 宽输入电压范围：±7mV 至 ±5V
  • 数据速率：2.5SPS 至 40kSPS
  • 2.5V 基准：2ppm/°C
  • 同步 50Hz 和 60Hz 抑制模式
  • 单周期稳定模式
  • 信号和基准监控器
  • 5V 或 ±2.5V 电源
  • 内部温度传感器
  • 循环冗余校验 (CRC)
  • 激励电流源
  • 传感器烧毁电流源
  • 四路通用输入/输出 (ADS1261)
  • 用于桥式传感器的交流激励 (ADS1261)
  • 5mm × 5mm VQFN 封装

2 应用

  • PLC 模拟输入模块
  • 称重秤和应变仪数字转换器
  • 温度、压力测量
  • 实验室仪表
  • 过程分析

3 说明

ADS1260 和 ADS1261(ADS126x) 均为包含可编程增益放大器 (PGA) 的精密 40kSPS ΔΣ 模数转换器 (ADC)。这些器件还包含精密的电压基准和内部故障监控器。这些支持传感器的 ADC 可以为要求最严苛的测量（包括称重秤和电阻式温度检测器 (RTD)）提供高精度单芯片解决方案。

这些 ADC 包含输入信号多路复用器、低噪声 PGA（提供 1 至 128 的增益）、4 位 ΔΣ 调制器、精密电压基准和可编程数字滤波器。

高阻抗 PGA 输入 (1GΩ) 可减小由传感器负载导致的测量误差。ADS1260 支持三路差分输入或五路单端输入。ADS1261 支持五路差分输入或十路单端输入。集成式电流源可简化 RTD 测量。

灵活的数字滤波器可针对单周期稳定转换进行编程，同时能够提供同步 50Hz 和 60Hz 线路周期抑制。信号和基准监控器、温度传感器和 CRC 数据验证可增强数据可靠性。

ADS126x 是引脚兼容的器件，采用 5mm × 5mm VQFN 封装，额定工作温度范围为 –40°C 至 +125°C。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
ADS126x VQFN (32) 5.0mm × 5.0mm
  1. 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附录。

Device Images

框图

ADS1260 ADS1261 ai_fbd_sbas760.gif

4 修订历史记录

Changes from B Revision (October 2018) to C Revision

  • Changed Figure 14, Offset Voltage Long-Term Drift to include 2000-hour data Go
  • Changed Figure 31, Voltage Reference Long-Term Drift to include 2000-hour data Go
  • Changed CRC polynomial to correct listing error: changed CRC-8-ATM (HEC): X8 + X2 + X0 + 1 to CRC-8-ATM (HEC): X8 + X2 + X1 + 1Go

Changes from A Revision (May 2018) to B Revision

  • Added 在产品说明书中添加了 ADS1261 器件Go
  • Changed 将 ADS1260 器件从预览更改成了生产数据（有效）Go
  • Added connection options to NC pinsGo
  • Added differential input current specification for gain = 128 in Electrical CharacteristicsGo
  • Added no missing codes specification in Electrical Characteristics Go
  • Changed integral nonlinearity specification for gain 64 and 128 in Electrical CharacteristicsGo
  • Changed integral nonlinearity specification for 40 kSPS mode in Electrical CharacteristicsGo
  • Added offset voltage long-term drift in Electrical CharacteristicsGo
  • Changed voltage reference inputs specification in Electrical Characteristics based on updated characteristicsGo
  • Added voltage reference initial error specification for ADS1260B and ADS1261B in Electrical CharacteristicsGo
  • Added voltage reference temperature drift specification for ADS1260B and ADS1261B in Electrical Characteristics Go
  • Added voltage reference long-term drift in Electrical Characteristics Go
  • Added voltage reference thermal hysteresis in Electrical CharacteristicsGo
  • Added note for PSRR calculation in Electrical CharacteristicsGo
  • Changed th(SCDO2) specification in Switching CharacteristicsGo
  • Changed tp(SCDO2) specification in Switching CharacteristicsGo
  • Added Figure 14, Offset Voltage Long-Term DriftGo
  • Changed Figure 24, Conversion Data Histogram (gain = 4) to 8192 data pointsGo
  • Changed Figure 25, Conversion Data Histogram (gain = 128) to 8192 data points Go
  • Changed Figure 27, Integral Nonlinearity vs Temperature based on updated characteristics Go
  • Changed Figure 28, Integral Nonlinearity Distribution to add gain = 128 Go
  • Changed Figure 29, Integral Nonlinearity vs Reference Voltage to add gain = 64 and 128 Go
  • Added Figure 30, Voltage Reference vs Temperature for ADS1260B, ADS1261B Go
  • Added Figure 31, Voltage Reference Long-Term DriftGo
  • Changed Figure 32, Reference Input Current vs Reference Voltage based on updated characteristicsGo
  • Added Figure 39, CMRR vs Frequency Go
  • Added Figure 40, PSRR vs Frequency Go
  • Added text for Table 2, Effective Resolution (Noise-Free Resolution)Go
  • Changed Table 2, Effective Resolution (Noise-Free Resolution) based on updated characteristicsGo

Changes from * Revision (March 2018) to A Revision

  • Changed 将 ADS1261 器件从预告信息更改成了生产数据（有效）Go

5 Device Comparison Table

PART NUMBER CHANNELS(1) VOLTAGE REFERENCE GRADE REFERENCE INPUTS GPIO
AC EXCITATION
SINGLE-ENDED DIFFERENTIAL
ADS1260B(2) 5 3 12 ppm/°C max 1 —
ADS1261B 10 5 12 ppm/°C max 2 4
ADS1261 10 5 40 ppm/°C max 2 4
(1) Reference inputs, GPIOs, and AC-excitation outputs are multiplexed with the analog input channels.
(2) The ADS1260 is available in B grade only.

6 Pin Configuration and Functions

RHB Package: ADS1260
VQFN-32
Top View
RHB Package: ADS1261
VQFN-32
Top View

Pin Functions

PIN TYPE DESCRIPTION
NO. ADS1260 ADS1261
1 AINCOM AINCOM Analog
input/output		 Analog input common, IDAC1, IDAC2, VBIAS
2 CAPP CAPP Analog output PGA output P; connect a 4.7-nF C0G dielectric capacitor across CAPP and CAPN
3 CAPN CAPN Analog output PGA output N; connect a 4.7-nF C0G dielectric capacitor across CAPP and CAPN
4 AVDD AVDD Analog Positive analog power supply
5 AVSS AVSS Analog Negative analog power supply
6 REFOUT REFOUT Analog output Internal 2.5-V reference output; connect a 10-µF capacitor to AVSS
7 PWDN PWDN Digital input Power down, active low
8 RESET RESET Digital input Reset, active low
9 START START Digital input Start conversion control, active high
10 CS CS Digital input Serial interface chip select, active low
11 SCLK SCLK Digital Input Serial interface shift clock
12 DIN DIN Digital Input Serial interface data input
13 DRDY DRDY Digital output Data ready indicator, active low
14 DOUT/DRDY DOUT/DRDY Digital output Dual function serial interface data output and active-low data ready indicator
15 BYPASS BYPASS Analog output Internal subregulator bypass; connect a 1-µF capacitor to DGND
16 DGND DGND Digital Digital ground
17 DVDD DVDD Digital Digital power supply
18 CLKIN CLKIN Digital input 1) Internal oscillator: connect to DGND
2) External clock: connect clock input
19-22 NC NC — No connection. Electrically float or connect to DGND
23 NC AIN9 Analog
input/output		 ADS1260: No connection. Electrically float or connect to DGND
ADS1261: Analog input 9, IDAC1, IDAC2
24 NC AIN8 Analog
input/output		 ADS1260: No connection. Electrically float or connect to DGND
ADS1261: Analog input 8, IDAC1, IDAC2
25 NC AIN7 Analog
input/output		 ADS1260: No connection. Electrically float or connect to DGND
ADS1261: Analog input 7, IDAC1, IDAC2
26 NC AIN6 Analog
input/output		 ADS1260: No connection. Electrically float or connect to DGND
ADS1261: Analog input 6, IDAC1, IDAC2
27 NC AIN5 Analog
input/output		 ADS1260: No connection. Electrically float or connect to DGND
ADS1261: Analog input 5, IDAC1, IDAC2, GPIO3, ACX2
28 AIN4 AIN4 Analog
input/output		 ADS1260: Analog input 4, IDAC1, IDAC2
ADS1261: Analog input 4, IDAC1, IDAC2, GPIO2, ACX1
29 AIN3 AIN3 Analog
input/output		 ADS1260: Analog input 3, IDAC1, IDAC2
ADS1261: Analog input 3, IDAC1, IDAC2, REFN1, GPIO1, ACX2
30 AIN2 AIN2 Analog
input/output		 ADS1260: Analog input 2, IDAC1, IDAC2
ADS1261: Analog input 2, IDAC1, IDAC2, REFP1, GPIO0, ACX1
31 AIN1 AIN1 Analog
input/output		 Analog input 1, IDAC1, IDAC2, REFN0
32 AIN0 AIN0 Analog
input/output		 Analog input 0, IDAC1, IDAC2, REFP0
Thermal Pad Pad Pad — Exposed thermal pad; Connect to AVSS. Pad must be soldered for mechanical integrity.

7 Specifications

 
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