ZHCSDJ6E February   2015  – June 2018 LMH1218

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化 SPI 电路原理图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
    2.     Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Loss of Signal Detector
      2. 7.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 7.3.3 2:1 Multiplexer
      4. 7.3.4 Clock and Data Recovery
      5. 7.3.5 Eye Opening Monitor (EOM)
      6. 7.3.6 Fast EOM
        1. 7.3.6.1 SMBus Fast EOM Operation
        2. 7.3.6.2 SPI Fast EOM Operation
      7. 7.3.7 LMH1218 Device Configuration
        1. 7.3.7.1 MODE_SEL
        2. 7.3.7.2 ENABLE
        3. 7.3.7.3 LOS_INT_N
        4. 7.3.7.4 LOCK
        5. 7.3.7.5 SMBus MODE
        6. 7.3.7.6 SMBus READ/WRITE Transaction
        7. 7.3.7.7 SPI Mode
          1. 7.3.7.7.1 SPI READ/WRITE Transaction
          2. 7.3.7.7.2 SPI Write Transaction Format
          3. 7.3.7.7.3 SPI Read Transaction Format
        8. 7.3.7.8 SPI Daisy Chain
          1. 7.3.7.8.1 SPI Daisy Chain Write Example
          2. 7.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 7.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 7.3.8 Power-On Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Global Registers
      2. 7.6.2 Receiver Registers
      3. 7.6.3 CDR Registers
      4. 7.6.4 Transmitter Registers
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for All Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Initialization Set Up
      1. 8.4.1 Selective Data Rate Lock
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Solder Profile
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息

SMBus MODE

The SMBus interface can also be used to control the device. If pin 1 (MODE_SEL) is pulled low through 1 kΩ to GND, then Pins 3, 4 are configured as the SMBUS_SCL and SMBUS_SDA respectively. Pins 2, 15 are address straps, ADDR0/ADDR1 respectively, during power up.

The maximum operating speed supported on the SMBus pins is 400 kHz.

Table 4. SMBus MODE

ADDR0 ADDR1 ADDR0 [BINARY] ADDR1 [BINARY] 7-Bit SLAVE
ADDRESS [HEX]
8-Bit WRITE
COMMAND [HEX]
1 kΩ to GND 1 kΩ to GND 00 00 0D 1A
1 kΩ to GND 20 kΩ to GND 00 01 0E 1C
1 kΩ to GND Float 00 10 0F 1E
1 kΩ to GND 1 kΩ to VDD 00 11 10 20
20 kΩ to GND 1 kΩ to GND 01 00 11 22
20 kΩ to GND 20 kΩ to GND 01 01 12 24
20 kΩ to GND Float 01 10 13 26
20 kΩ to GND 1 kΩ to VDD 01 11 14 28
Float 1 kΩ to GND 10 00 15 2A
Float 20 kΩ to GND 10 01 16 2C
Float Float 10 10 17 2E
Float 1 kΩ to VDD 10 11 18 30
1 kΩ to VDD 1 kΩ to GND 11 00 19 32
1 kΩ to VDD 20 kΩ to GND 11 01 1A 34
1 kΩ to VDD Float 11 10 1B 36
1 kΩ to VDD 1 kΩ to VDD 11 11 1C 38

Note: These are 7 bit addresses. Therefore, the LSB must be added to indicate read/write. LSB equal to zero indicates write and 1 indicates SMBus read operation. For example, for 7 bit hex address 0x0D, the I2C hex address byte is 0x1A to write and 0X1B to read.