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  • TMS320F2805x 实时微控制器

    • ZHCSAH6F November   2012  – September 2021 TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28053 , TMS320F28054 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F28055

      PRODUCTION DATA  

  • CONTENTS
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  • TMS320F2805x 实时微控制器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 功能方框图
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT
      2. 7.5.2 Reducing Current Consumption
      3. 7.5.3 Current Consumption Graphs (VREG Enabled)
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for PN Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  JTAG Debug Probe Connection Without Signal Buffering for the MCU
    10. 7.10 Parameter Information
      1. 7.10.1 Timing Parameter Symbology
      2. 7.10.2 General Notes on Timing Parameters
    11. 7.11 Test Load Circuit
    12. 7.12 Power Sequencing
      1. 7.12.1 Reset ( XRS) Timing Requirements
      2. 7.12.2 Reset ( XRS) Switching Characteristics
    13. 7.13 Clock Specifications
      1. 7.13.1 Device Clock Table
        1. 7.13.1.1 2805x Clock Table and Nomenclature (60-MHz Devices)
        2. 7.13.1.2 Device Clocking Requirements/Characteristics
        3. 7.13.1.3 Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics
      2. 7.13.2 Clock Requirements and Characteristics
        1. 7.13.2.1 XCLKIN Timing Requirements - PLL Enabled
        2. 7.13.2.2 XCLKIN Timing Requirements - PLL Disabled
        3. 7.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 7.14 Flash Timing
      1. 7.14.1 Flash/OTP Endurance for T Temperature Material
      2. 7.14.2 Flash/OTP Endurance for S Temperature Material
      3. 7.14.3 Flash/OTP Endurance for Q Temperature Material
      4. 7.14.4 Flash Parameters at 60-MHz SYSCLKOUT
      5. 7.14.5 Flash/OTP Access Timing
      6. 7.14.6 Flash Data Retention Duration
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  CPU
      2. 8.1.2  Control Law Accelerator
      3. 8.1.3  Memory Bus (Harvard Bus Architecture)
      4. 8.1.4  Peripheral Bus
      5. 8.1.5  Real-Time JTAG and Analysis
      6. 8.1.6  Flash
      7. 8.1.7  M0, M1 SARAMs
      8. 8.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 8.1.9  Boot ROM
        1. 8.1.9.1 Emulation Boot
        2. 8.1.9.2 GetMode
        3. 8.1.9.3 Peripheral Pins Used by the Bootloader
      10. 8.1.10 Security
      11. 8.1.11 Peripheral Interrupt Expansion Block
      12. 8.1.12 External Interrupts (XINT1 to XINT3)
      13. 8.1.13 Internal Zero-Pin Oscillators, Oscillator, and PLL
      14. 8.1.14 Watchdog
      15. 8.1.15 Peripheral Clocking
      16. 8.1.16 Low-power Modes
      17. 8.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 8.1.18 General-Purpose Input/Output Multiplexer
      19. 8.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 8.1.20 Control Peripherals
      21. 8.1.21 Serial Port Peripherals
    2. 8.2 Memory Maps
    3. 8.3 Register Map
    4. 8.4 Device Emulation Registers
    5. 8.5 VREG, BOR, POR
      1. 8.5.1 On-chip VREG
        1. 8.5.1.1 Using the On-chip VREG
        2. 8.5.1.2 Disabling the On-chip VREG
      2. 8.5.2 On-chip Power-On Reset and Brownout Reset Circuit
    6. 8.6 System Control
      1. 8.6.1 Internal Zero-Pin Oscillators
      2. 8.6.2 Crystal Oscillator Option
      3. 8.6.3 PLL-Based Clock Module
      4. 8.6.4 Loss of Input Clock (NMI-watchdog Function)
      5. 8.6.5 CPU-watchdog Module
    7. 8.7 Low-power Modes Block
    8. 8.8 Interrupts
      1. 8.8.1 External Interrupts
        1. 8.8.1.1 External Interrupt Electrical Data/Timing
          1. 8.8.1.1.1 External Interrupt Timing Requirements
          2. 8.8.1.1.2 External Interrupt Switching Characteristics
    9. 8.9 Peripherals
      1. 8.9.1  Control Law Accelerator
        1. 8.9.1.1 CLA Device-Specific Information
        2. 8.9.1.2 CLA Register Descriptions
      2. 8.9.2  Analog Block
        1. 8.9.2.1 Analog-to-Digital Converter
          1. 8.9.2.1.1 ADC Device-Specific Information
          2. 8.9.2.1.2 ADC Electrical Data/Timing
            1. 8.9.2.1.2.1 ADC Electrical Characteristics
            2. 8.9.2.1.2.2 ADC Power Modes
            3. 8.9.2.1.2.3 External ADC Start-of-Conversion Electrical Data/Timing
              1. 8.9.2.1.2.3.1 External ADC Start-of-Conversion Switching Characteristics
            4. 8.9.2.1.2.4 Internal Temperature Sensor
              1. 8.9.2.1.2.4.1 Temperature Sensor Coefficient
            5. 8.9.2.1.2.5 ADC Power-Up Control Bit Timing
              1. 8.9.2.1.2.5.1 ADC Power-Up Delays
            6. 8.9.2.1.2.6 ADC Sequential and Simultaneous Timings
        2. 8.9.2.2 Analog Front End
          1. 8.9.2.2.1 AFE Device-Specific Information
          2. 8.9.2.2.2 AFE Register Descriptions
          3. 8.9.2.2.3 PGA Electrical Data/Timing
          4. 8.9.2.2.4 Comparator Block Electrical Data/Timing
            1. 8.9.2.2.4.1 Electrical Characteristics of the Comparator/DAC
          5. 8.9.2.2.5 VREFOUT Buffered DAC Electrical Data
            1. 8.9.2.2.5.1 Electrical Characteristics of VREFOUT Buffered DAC
      3. 8.9.3  Detailed Descriptions
      4. 8.9.4  Serial Peripheral Interface
        1. 8.9.4.1 SPI Device-Specific Information
        2. 8.9.4.2 SPI Register Descriptions
        3. 8.9.4.3 SPI Master Mode Electrical Data/Timing
          1. 8.9.4.3.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 8.9.4.3.2 SPI Master Mode External Timing (Clock Phase = 1)
        4. 8.9.4.4 SPI Slave Mode Electrical Data/Timing
          1. 8.9.4.4.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 8.9.4.4.2 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 8.9.5  Serial Communications Interface
        1. 8.9.5.1 SCI Device-Specific Information
        2. 8.9.5.2 SCI Register Descriptions
      6. 8.9.6  Enhanced Controller Area Network
        1. 8.9.6.1 eCAN Device-Specific Information
        2. 8.9.6.2 eCAN Register Descriptions
      7. 8.9.7  Inter-Integrated Circuit
        1. 8.9.7.1 I2C Device-Specific Information
        2. 8.9.7.2 I2C Register Descriptions
        3. 8.9.7.3 I2C Electrical Data/Timing
          1. 8.9.7.3.1 I2C Timing Requirements
          2. 8.9.7.3.2 I2C Switching Characteristics
      8. 8.9.8  Enhanced Pulse Width Modulator
        1. 8.9.8.1 ePWM Device-Specific Information
        2. 8.9.8.2 ePWM Register Descriptions
        3. 8.9.8.3 ePWM Electrical Data/Timing
          1. 8.9.8.3.1 ePWM Timing Requirements
          2. 8.9.8.3.2 ePWM Switching Characteristics
          3. 8.9.8.3.3 Trip-Zone Input Timing
            1. 8.9.8.3.3.1 Trip-Zone Input Timing Requirements
      9. 8.9.9  Enhanced Capture Module
        1. 8.9.9.1 eCAP Module Device-Specific Information
        2. 8.9.9.2 eCAP Module Register Descriptions
        3. 8.9.9.3 eCAP Module Electrical Data/Timing
          1. 8.9.9.3.1 eCAP Timing Requirement
          2. 8.9.9.3.2 eCAP Switching Characteristics
      10. 8.9.10 Enhanced Quadrature Encoder Pulse
        1. 8.9.10.1 eQEP Device-Specific Information
        2. 8.9.10.2 eQEP Register Descriptions
        3. 8.9.10.3 eQEP Electrical Data/Timing
          1. 8.9.10.3.1 eQEP Timing Requirements
          2. 8.9.10.3.2 eQEP Switching Characteristics
      11. 8.9.11 JTAG Port
        1. 8.9.11.1 JTAG Port Device-Specific Information
      12. 8.9.12 General-Purpose Input/Output
        1. 8.9.12.1 GPIO Device-Specific Information
        2. 8.9.12.2 GPIO Register Descriptions
        3. 8.9.12.3 GPIO Electrical Data/Timing
          1. 8.9.12.3.1 GPIO - Output Timing
            1. 8.9.12.3.1.1 General-Purpose Output Switching Characteristics
          2. 8.9.12.3.2 GPIO - Input Timing
            1. 8.9.12.3.2.1 General-Purpose Input Timing Requirements
          3. 8.9.12.3.3 Sampling Window Width for Input Signals
          4. 8.9.12.3.4 Low-Power Mode Wakeup Timing
            1. 8.9.12.3.4.1 IDLE Mode Timing Requirements
            2. 8.9.12.3.4.2 IDLE Mode Switching Characteristics
            3. 8.9.12.3.4.3 STANDBY Mode Timing Requirements
            4. 8.9.12.3.4.4 STANDBY Mode Switching Characteristics
            5. 8.9.12.3.4.5 HALT Mode Timing Requirements
            6. 8.9.12.3.4.6 HALT Mode Switching Characteristics
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 术语表
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
  12. 重要声明
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DATA SHEET

TMS320F2805x 实时微控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 高效 32 位 CPU (TMS320C28x)
    • 60MHz（16.67ns 周期时间）
    • 16 × 16 和 32 × 32 乘法和累加 (MAC) 运算
    • 16 × 16 双 MAC
    • 哈佛 (Harvard) 总线架构
    • 连动运算
    • 快速中断响应和处理
    • 统一存储器编程模型
    • 高效代码（使用 C/C++ 和汇编语言）
  • 可编程控制律加速器 (CLA)
    • 32 位浮点数学加速器
    • 独立于主 CPU 之外的代码执行
  • 双区域安全模块
  • 字节序：小端字节序
  • 低器件和系统成本：
    • 3.3V 单电源
    • 无需电源排序
    • 集成型加电复位和欠压复位
    • 低功耗
    • 无模拟支持引脚
  • 时钟：
    • 两个内部零引脚振荡器
    • 片上晶振振荡器和外部时钟输入
    • 看门狗计时器模块
    • 丢失时钟检测电路
  • 多达 42 个具有输入滤波功能的独立可编程、多路复用通用输入/输出 (GPIO) 引脚
  • 支持 JTAG 边界扫描
    • IEEE 标准 1149.1-1990 标准测试访问端口和边界扫描架构
  • 可支持所有外设中断的外设中断扩展 (PIE) 模块
  • 三个 32 位 CPU 计时器
  • 每个 ePWM 模块中的独立 16 位计时器
  • 片上存储器
    • 可提供闪存、SARAM、消息 RAM、OTP、CLA 数据 ROM、引导 ROM、安全 ROM
  • 128 位安全密钥和锁
    • 保护安全内存块
    • 防止固件逆向工程
  • 串行端口外设
    • 三个串行通信接口 (SCI)（通用异步接收器/发送器 [UART]）模块
    • 一个串行外设接口 (SPI) 模块
    • 一条内部集成电路 (I2C) 总线
    • 一条增强型控制器局域网络 (eCAN) 总线
  • 增强型控制外设
    • 增强型脉宽调制器 (ePWM)
    • 增强型捕捉 (eCAP) 模块
    • 增强型正交编码器脉冲 (eQEP) 模块
  • 模拟外设
    • 一个 12 位模数转换器 (ADC)
    • 一个用于振荡器补偿的片上温度传感器
    • 多达七个比较器，这些比较器具有多达三个集成型数模转换器 (DAC)
    • 一个经缓冲的基准 DAC
    • 多达四个可编程增益放大器 (PGA)
    • 多达四个数字滤波器
  • 高级调试特性
    • 分析和断点功能
    • 通过硬件进行实时调试
  • 80 引脚 PN Low-Profile Quad Flatpack (LQFP)
  • 温度选项
    • T：–40°C 至 105°C
    • S：–40°C 至 125°C
    • Q：–40°C 至 125°C 的环境温度范围
      （通过针对汽车应用的 AEC Q100 认证）

2 应用

  • 空调室外机
  • 电梯门自动启闭装置驱动控制
  • 逆变器和电机控制
  • 交流驱动器控制模块
  • 交流输入 BLDC 电机驱动器
  • 直流输入 BLDC 电机驱动器

3 说明

C2000™ 实时控制 MCU 针对处理、感应和驱动进行了优化，可提高实时控制应用（如工业电机驱动器、光伏逆变器和数字电源、电动汽车和运输、电机控制以及感应和信号处理）的闭环性能。C2000 系列包括高级性能 MCU 和入门级性能 MCU。

F2805x 系列微控制器 (MCU) 为 C28x 内核以及与引脚较少的器件中高度集成的控制外设耦合的 CLA 供电。该系列器件的代码与基于 C28x 的旧版代码兼容，同时具有较高的模拟集成度。

一个内部稳压器实现了单电源轨运行。增设了具有 6 位内部基准的模拟比较器，并可通过与其直接连接来控制 PWM 输出。ADC 可在 0V 至 3.3V 的固定满量程范围内实施转换，支持 VREFHI/VREFLO 基准的比例运算。ADC 接口已针对低开销和延迟进行了优化。

模拟前端 (AFE) 含有多达七个比较器以及多达三个集成 DAC、一个 VREFOUT 缓冲 DAC、多达四个 PGA 以及多达四个数字滤波器。PGA 可以采用三种离散增益模式放大输入信号。AFE 外设的实际数量将取决于 TMS320F2805x 器件数量。请参阅器件比较了解更多详细信息

要了解有关 C2000 MCU 的更多信息，请访问 C2000™ 实时控制 MCU 页面。

器件信息
器件型号(1) 封装 封装尺寸
TMS320F28055PN LQFP (80) 12.0mm × 12.0mm
TMS320F28054PN LQFP (80) 12.0mm × 12.0mm
TMS320F28053PN LQFP (80) 12.0mm × 12.0mm
TMS320F28052PN LQFP (80) 12.0mm × 12.0mm
TMS320F28051PN LQFP (80) 12.0mm × 12.0mm
TMS320F28050PN LQFP (80) 12.0mm × 12.0mm
(1) 如需这些器件的详细信息，请参阅机械、封装和可订购信息。

3.1 功能方框图

GUID-C3462EBB-7292-427D-B41D-C42EC9456AF4-low.gif
在所有器件上存储安全复制代码函数。
由于多路复用，所有外设引脚不能同时使用。
图 3-1 功能方框图

4 Revision History

Changes from February 2, 2021 to September 13, 2021 (from Revision E (February 2021) to Revision F (September 2021))

  • Table 5-1, Device Comparison: Changed "SCI" to "SCI/UART". Updated footnote about TMS320F2805xM and TMS320F2805xF. Added device numbers in Temperature options section. Go
  • Section 6.2.1, Signal Descriptions: Updated DESCRIPTION of VREGENZ.Go
  • Section 7.2, ESD Ratings – Commercial: Updated device numbers.Go
  • Section 7.3, ESD Ratings – Automotive: Updated device numbers.Go
  • Section 7.13.1.3, Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics: Updated footnote about oscillator frequency.Go
  • Section 8.1.10, Security: Updated section.Go
  • Figure 8-1, 28055 and 28054 Memory Map: Changed “Secure Zone + ECSL” to “Secure Zone”.Go
  • Figure 8-2, 28053 and 28052 Memory Map: Changed “Secure Zone + ECSL” to “Secure Zone”.Go
  • Figure 8-3, 28051 Memory Map: Changed “Secure Zone + ECSL” to “Secure Zone”.Go
  • Figure 8-4, 28050 Memory Map: Changed “Secure Zone + ECSL” to “Secure Zone”.Go
  • Section 10.1, Getting Started: Updated reference page link.Go
  • Section 10.3, Tools and Software: Updated section.Go

5 Device Comparison

Table 5-1 lists the features of the TMS320F2805x devices.

Table 5-1 Device Comparison
FEATURE 28055
(60 MHz)		 28054
28054-Q1
28054M(1)
28054M-Q1
28054F(1)
28054F-Q1
(60 MHz)		 28053
(60 MHz)		 28052
28052-Q128052M(1)
28052M-Q1
28052F(1)
28052F-Q1
(60 MHz)		 28051
(60 MHz)		 28050
(60 MHz)
Package type 80-pin PN
LQFP		 80-pin PN
LQFP		 80-pin PN
LQFP		 80-pin PN
LQFP		 80-pin PN
LQFP		 80-pin PN
LQFP
Instruction cycle 16.67 ns 16.67 ns 16.67 ns 16.67 ns 16.67 ns 16.67 ns
CLA Yes No Yes No No No
On-chip flash (16-bit word) 64K 64K 32K 32K 32K 16K
On-chip SARAM (16-bit word) 10K 10K (28054)
8K (28054M)
8K (28054F)		 10K 10K (28052)
8K (28052M)
8K (28052F)		 8K 6K
Dual-zone security for on-chip flash, SARAM, OTP, and secure ROM blocks Yes Yes Yes Yes Yes Yes
Boot ROM (12K × 16) Yes Yes Yes Yes Yes Yes
One-time programmable (OTP) ROM
(16-bit word)		 1K 1K 1K 1K 1K 1K
ePWM channels 14 14 14 14 14 14
eCAP inputs 1 1 1 1 1 1
eQEP modules 1 1 1 1 1 1
Watchdog timer Yes Yes Yes Yes Yes Yes
12-Bit ADC MSPS 3.75 3.75 3.75 3.75 2 2
Conversion time 267 ns 267 ns 267 ns 267 ns 500 ns 500 ns
Channels 16 16 16 16 16 16
Temperature sensor Yes Yes Yes Yes Yes Yes
Dual
sample-and-hold		 Yes Yes Yes Yes Yes Yes
PGA (Gain ≈ 3, 6, or 11) 4 4 4 4 4 3
Fixed Gain Amplifier (Gain ≈ 3) 3 3 3 3 3 4
Comparators 7 7 7 7 7 6
Internal comparator reference DACs 3 3 3 3 3 2
Buffered reference DAC 1 1 1 1 1 1
32-Bit CPU timers 3 3 3 3 3 3
I2C 1 1 1 1 1 1
eCAN 1 1 1 1 1 1
SPI 1 1 1 1 1 1
SCI/UART 3 3 3 3 3 3
0-pin oscillators 2 2 2 2 2 2
I/O pins (shared) GPIO 42 42 42 42 42 42
External interrupts 3 3 3 3 3 3
Supply voltage (nominal) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Temperature options T: –40°C to 105°C 28055 28054
28054M
28054F		 28053 28052
28052M
28052F		 28051 28050
S: –40°C to 125°C 28055 28054 only 28053 28052 only 28051 28050
Q: –40°C to 125°C(2) – 28054-Q1
28054M-Q1
28054F-Q1		 – 28052-Q1
28052M-Q1
28052F-Q1		 – –
(1) TMS320F2805xF devices are InstaSPIN-FOC-enabled MCUs. TMS320F2805xM devices are InstaSPIN-MOTION-enabled MCUs. However, InstaSPIN-MOTION is no longer recommended for new designs and will not have application support. On these devices, TI has secured Zone1 and allocated RAML0 to Zone1. Because of this, Zone1 and RAML0 are not available for customer applications; only Zone2 is available. For more information, see Section 10.4 for a list of InstaSPIN Technical Reference Manuals.
(2) The letter Q refers to AEC Q100 qualification for automotive applications.

5.1 Related Products

For information about similar products, see the following links:

TMS320F2802x Real-Time Microcontrollers
The F2802x series offers the lowest pin-count and Flash memory size options. InstaSPIN-FOC™ versions are available.

TMS320F2803x Real-Time Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the parallel control law accelerator (CLA) option.

TMS320F2805x Real-Time Microcontrollers
The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs). InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.

TMS320F2806x Real-Time Microcontrollers
The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the pin-count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-MOTION™ versions are available.

TMS320F2807x Real-Time Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options. The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.

TMS320F28004x Real-Time Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements. InstaSPIN-FOC and configurable logic block (CLB) versions are available.

6 Terminal Configuration and Functions

6.1 Pin Diagram

Figure 6-1 shows the 80-pin PN Low-Profile Quad Flatpack pin assignments.

GUID-79735484-ADEC-4191-A9B4-7B13A90B2D80-low.gifFigure 6-1 2805x 80-Pin PN Low-Profile Quad Flatpack (Top View)

 
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