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  • TMS320F2806x 实时微控制器

    • ZHCS009J November   2010  – September 2021 TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1

      PRODUCTION DATA  

  • CONTENTS
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  • TMS320F2806x 实时微控制器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 功能方框图
    2. 3.2 系统器件图
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT
      2. 7.5.2 Reducing Current Consumption
      3. 7.5.3 Current Consumption Graphs (VREG Enabled)
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics
      1. 7.7.1 PFP PowerPAD Package
      2. 7.7.2 PZP PowerPAD Package
      3. 7.7.3 PN Package
      4. 7.7.4 PZ Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Debug Probe Connection Without Signal Buffering for the MCU
    10. 7.10 Parameter Information
      1. 7.10.1 Timing Parameter Symbology
      2. 7.10.2 General Notes on Timing Parameters
    11. 7.11 Test Load Circuit
    12. 7.12 Power Sequencing
      1. 7.12.1 Reset ( XRS) Timing Requirements
      2. 7.12.2 Reset ( XRS) Switching Characteristics
    13. 7.13 Clock Specifications
      1. 7.13.1 Device Clock Table
        1. 7.13.1.1 2806x Clock Table and Nomenclature (90-MHz Devices)
        2. 7.13.1.2 Device Clocking Requirements/Characteristics
        3. 7.13.1.3 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 7.13.2 Clock Requirements and Characteristics
        1. 7.13.2.1 XCLKIN Timing Requirements – PLL Enabled
        2. 7.13.2.2 XCLKIN Timing Requirements – PLL Disabled
        3. 7.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 7.14 Flash Timing
      1. 7.14.1 Flash/OTP Endurance for T Temperature Material
      2. 7.14.2 Flash/OTP Endurance for S Temperature Material
      3. 7.14.3 Flash/OTP Endurance for Q Temperature Material
      4. 7.14.4 Flash Parameters at 90-MHz SYSCLKOUT
      5. 7.14.5 Flash/OTP Access Timing
      6. 7.14.6 Flash Data Retention Duration
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  CPU
      2. 8.1.2  Control Law Accelerator (CLA)
      3. 8.1.3  Viterbi, Complex Math, CRC Unit (VCU)
      4. 8.1.4  Memory Bus (Harvard Bus Architecture)
      5. 8.1.5  Peripheral Bus
      6. 8.1.6  Real-Time JTAG and Analysis
      7. 8.1.7  Flash
      8. 8.1.8  M0, M1 SARAMs
      9. 8.1.9  L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs
      10. 8.1.10 Boot ROM
        1. 8.1.10.1 Debug Boot
        2. 8.1.10.2 GetMode
        3. 8.1.10.3 Peripheral Pins Used by the Bootloader
      11. 8.1.11 Security
      12. 8.1.12 Peripheral Interrupt Expansion (PIE) Block
      13. 8.1.13 External Interrupts (XINT1 to XINT3)
      14. 8.1.14 Internal Zero Pin Oscillators, Oscillator, and PLL
      15. 8.1.15 Watchdog
      16. 8.1.16 Peripheral Clocking
      17. 8.1.17 Low-power Modes
      18. 8.1.18 Peripheral Frames 0, 1, 2, 3 (PFn)
      19. 8.1.19 General-Purpose Input/Output (GPIO) Multiplexer
      20. 8.1.20 32-Bit CPU-Timers (0, 1, 2)
      21. 8.1.21 Control Peripherals
      22. 8.1.22 Serial Port Peripherals
    2. 8.2 Memory Maps
    3. 8.3 Register Maps
    4. 8.4 Device Debug Registers
    5. 8.5 VREG, BOR, POR
      1. 8.5.1 On-chip VREG
        1. 8.5.1.1 Using the On-chip VREG
        2. 8.5.1.2 Disabling the On-chip VREG
      2. 8.5.2 On-chip Power-On Reset (POR) and Brownout Reset (BOR) Circuit
    6. 8.6 System Control
      1. 8.6.1 Internal Zero Pin Oscillators
      2. 8.6.2 Crystal Oscillator Option
      3. 8.6.3 PLL-Based Clock Module
      4. 8.6.4 USB and HRCAP PLL Module (PLL2)
      5. 8.6.5 Loss of Input Clock (NMI Watchdog Function)
      6. 8.6.6 CPU Watchdog Module
    7. 8.7 Low-power Modes Block
    8. 8.8 Interrupts
      1. 8.8.1 External Interrupts
        1. 8.8.1.1 External Interrupt Electrical Data/Timing
          1. 8.8.1.1.1 External Interrupt Timing Requirements
          2. 8.8.1.1.2 External Interrupt Switching Characteristics
    9. 8.9 Peripherals
      1. 8.9.1  CLA Overview
      2. 8.9.2  Analog Block
        1. 8.9.2.1 Analog-to-Digital Converter (ADC)
          1. 8.9.2.1.1 Features
          2. 8.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. 8.9.2.1.2.1 External ADC Start-of-Conversion Switching Characteristics
          3. 8.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. 8.9.2.1.3.1 ADC Electrical Characteristics
            2. 8.9.2.1.3.2 ADC Power Modes
            3. 8.9.2.1.3.3 Internal Temperature Sensor
              1. 8.9.2.1.3.3.1 Temperature Sensor Coefficient
            4. 8.9.2.1.3.4 ADC Power-Up Control Bit Timing
              1. 8.9.2.1.3.4.1 ADC Power-Up Delays
            5. 8.9.2.1.3.5 ADC Sequential and Simultaneous Timings
        2. 8.9.2.2 ADC MUX
        3. 8.9.2.3 Comparator Block
          1. 8.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. 8.9.2.3.1.1 Electrical Characteristics of the Comparator/DAC
      3. 8.9.3  Detailed Descriptions
      4. 8.9.4  Serial Peripheral Interface (SPI) Module
        1. 8.9.4.1 SPI Master Mode Electrical Data/Timing
          1. 8.9.4.1.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 8.9.4.1.2 SPI Master Mode External Timing (Clock Phase = 1)
        2. 8.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. 8.9.4.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 8.9.4.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 8.9.5  Serial Communications Interface (SCI) Module
      6. 8.9.6  Multichannel Buffered Serial Port (McBSP) Module
        1. 8.9.6.1 McBSP Electrical Data/Timing
          1. 8.9.6.1.1 McBSP Transmit and Receive Timing
            1. 8.9.6.1.1.1 McBSP Timing Requirements
            2. 8.9.6.1.1.2 McBSP Switching Characteristics
          2. 8.9.6.1.2 McBSP as SPI Master or Slave Timing
            1. 8.9.6.1.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 8.9.6.1.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 8.9.6.1.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. 8.9.6.1.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 8.9.6.1.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. 8.9.6.1.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 8.9.6.1.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. 8.9.6.1.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      7. 8.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 8.9.8  Inter-Integrated Circuit (I2C)
        1. 8.9.8.1 I2C Electrical Data/Timing
          1. 8.9.8.1.1 I2C Timing Requirements
          2. 8.9.8.1.2 I2C Switching Characteristics
      9. 8.9.9  Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)
        1. 8.9.9.1 ePWM Electrical Data/Timing
          1. 8.9.9.1.1 ePWM Timing Requirements
          2. 8.9.9.1.2 ePWM Switching Characteristics
        2. 8.9.9.2 Trip-Zone Input Timing
          1. 8.9.9.2.1 Trip-Zone Input Timing Requirements
      10. 8.9.10 High-Resolution PWM (HRPWM)
        1. 8.9.10.1 HRPWM Electrical Data/Timing
          1. 8.9.10.1.1 High-Resolution PWM Characteristics
      11. 8.9.11 Enhanced Capture Module (eCAP1)
        1. 8.9.11.1 eCAP Electrical Data/Timing
          1. 8.9.11.1.1 Enhanced Capture (eCAP) Timing Requirement
          2. 8.9.11.1.2 eCAP Switching Characteristics
      12. 8.9.12 High-Resolution Capture Modules (HRCAP1 to HRCAP4)
        1. 8.9.12.1 HRCAP Electrical Data/Timing
          1. 8.9.12.1.1 High-Resolution Capture (HRCAP) Timing Requirements
      13. 8.9.13 Enhanced Quadrature Encoder Modules (eQEP1, eQEP2)
        1. 8.9.13.1 eQEP Electrical Data/Timing
          1. 8.9.13.1.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. 8.9.13.1.2 eQEP Switching Characteristics
      14. 8.9.14 JTAG Port
      15. 8.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 8.9.15.1 GPIO Electrical Data/Timing
          1. 8.9.15.1.1 GPIO Output Timing
            1. 8.9.15.1.1.1 General-Purpose Output Switching Characteristics
          2. 8.9.15.1.2 GPIO Input Timing
            1. 8.9.15.1.2.1 General-Purpose Input Timing Requirements
          3. 8.9.15.1.3 Sampling Window Width for Input Signals
          4. 8.9.15.1.4 Low-Power Mode Wakeup Timing
            1. 8.9.15.1.4.1 IDLE Mode Timing Requirements
            2. 8.9.15.1.4.2 IDLE Mode Switching Characteristics
            3. 8.9.15.1.4.3 STANDBY Mode Timing Requirements
            4. 8.9.15.1.4.4 STANDBY Mode Switching Characteristics
            5. 8.9.15.1.4.5 HALT Mode Timing Requirements
            6. 8.9.15.1.4.6 HALT Mode Switching Characteristics
      16. 8.9.16 Universal Serial Bus (USB)
        1. 8.9.16.1 USB Electrical Data/Timing
          1. 8.9.16.1.1 USB Input Ports DP and DM Timing Requirements
          2. 8.9.16.1.2 USB Output Ports DP and DM Switching Characteristics
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
  12. 重要声明
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DATA SHEET

TMS320F2806x 实时微控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 高效 32 位 CPU (TMS320C28x)
    • 90MHz（11.11ns 周期时间）
    • 16 × 16 和 32 × 32 乘法和累加 (MAC) 运算
    • 16 × 16 双 MAC
    • 哈佛 (Harvard) 总线架构
    • 连动运算
    • 快速中断响应和处理
    • 统一存储器编程模型
    • 高效代码（使用 C/C++ 和汇编语言）
  • 浮点单元 (FPU)
    • 原生单精度浮点运算
  • 可编程控制律加速器 (CLA)
    • 32 位浮点数学加速器
    • 独立于主 CPU 之外的代码执行
  • Viterbi、复杂数学、CRC 单元 (VCU)
    • 扩展了 C28x 指令集以支持复杂的乘法、Viterbi 运算和循环冗余校验 (CRC)
  • 嵌入式存储器
    • 高达 256KB 的闪存
    • 高达 100KB 的随机存取存储器 (RAM)
    • 2KB 一次性可编程 (OTP) ROM
  • 6 通道直接内存存取 (DMA)
  • 低器件和系统成本
    • 3.3V 单电源
    • 无需电源排序
    • 集成型加电复位和欠压复位
    • 低功耗操作模式
    • 无模拟支持引脚
  • 字节序：小端字节序
  • 支持 JTAG 边界扫描
    • IEEE 标准 1149.1-1990 标准测试访问端口和边界扫描架构
  • 计时
    • 两个内部零引脚振荡器
    • 片载晶体振荡器/外部时钟输入
    • 看门狗计时器模块
    • 丢失时钟检测电路
  • 可支持所有外设中断的外设中断扩展 (PIE) 模块
  • 三个 32 位 CPU 计时器
  • 高级控制外设
  • 多达 8 个增强型脉冲宽度调制器 (ePWM) 模块
    • 总共 16 个 PWM 通道（可支持 8 个 HRPWM）
    • 每个模块中的独立 16 位计时器
  • 3 个输入增强型捕捉 (eCAP) 模块
  • 多达 4 个高分辨率捕捉 (HRCAP) 模块
  • 多达 2 个增强型正交编码器脉冲 (eQEP) 模块
  • 12 位模数转换器 (ADC)，具有双路采样保持 (S/H) 功能
    • 高达 3.46MSPS
    • 高达 16 通道
  • 片上温度传感器
  • 128 位安全密钥和锁
    • 保护安全内存块
    • 防止固件逆向工程
  • 串行端口外设
    • 两个串行通信接口 (SCI) [UART] 模块
    • 两个串行外设接口 (SPI) 模块
    • 一条内部集成电路 (I2C) 总线
    • 一个多通道缓冲串行端口 (McBSP) 总线
    • 一个增强型控制器局域网络 (eCAN)
    • 通用串行总线 (USB) 2.0
      （关于可用性，请参阅器件比较表）
      • 全速器件模式
      • 全速或低速主机模式
  • 多达 54 个具有输入滤波功能的独立可编程、多路复用通用输入/输出 (GPIO) 引脚
  • 高级调试特性
    • 分析和断点功能
    • 通过硬件进行实时调试
  • 封装选项
    • 80 引脚 PFP 和 100 引脚 PZP PowerPAD™ 耐热增强型薄型四方扁平封装 (HTQFP)
    • 80 引脚 PN 和 100 引脚 PZ 薄型四方扁平封装 (LQFP)
  • 温度选项
    • T：–40°C 至 105°C
    • S：–40°C 至 125°C
    • Q：–40°C 至 125°C 的环境温度范围（通过针对汽车应用的 AEC Q100 认证）

2 应用

  • 空调室外机
  • 电梯门自动启闭装置驱动控制
  • 逆变器和电机控制
  • 车载充电器 (OBC) 和无线充电器
  • 自动分拣设备
  • CNC 控制
  • 纺织机
  • 焊接机
  • 电动汽车充电站电源模块
  • 车辆无线充电模块
  • 能量存储电源转换系统 (PCS)
  • 中央逆变器
  • 微型逆变器
  • 太阳能电源优化器
  • 串式逆变器
  • 交流驱动器控制模块
  • 交流驱动器功率级模块
  • 线性电机功率级
  • 伺服驱动器控制模块
  • 伺服驱动器功率级模块
  • 交流输入 BLDC 电机驱动器
  • 直流输入 BLDC 电机驱动器
  • 工业交流-直流
  • 三相 UPS

3 说明

C2000™ 32 位微控制器针对处理、感应和驱动进行了优化，可提高实时控制应用（如工业电机驱动器、光伏逆变器和数字电源、电动汽车和运输、电机控制以及感应和信号处理）的闭环性能。C2000 系列包括高级性能 MCU 和入门级性能 MCU。

F2806x 系列微控制器 (MCU) 为 C28x 内核以及与引脚较少的器件中高度集成的控制外设耦合的 CLA 供电。该系列器件的代码与基于 C28x 的旧版代码兼容，同时具有较高的模拟集成度。

一个内部稳压器实现了单电源轨运行。对 HRPWM 模块实施了改进，以提供双边缘控制 （调频）。器件内还新增了采用 10 位内部基准的模拟比较器，可通过与其直接相连来控制 ePWM 输出。ADC 可在 0V 至 3.3V 的固定满量程范围内实施转换，支持 VREFHI/VREFLO 基准的比例运算。ADC 接口已针对低开销和延迟进行了优化。

如需详细了解 C2000 MCU，请访问“C2000 概述”，地址为 www.ti.com/c2000。

器件信息
器件型号(1) 封装 封装尺寸
TMS320F28069PZP HTQFP (100) 14.0mm × 14.0mm
TMS320F28069PFP HTQFP (80) 12.0mm x 12.0mm
TMS320F28069PZ LQFP (100) 14.0mm x 14.0mm
TMS320F28069PN LQFP (80) 12.0mm × 12.0mm
(1) 如需这些器件的详细信息，请参阅机械、封装和可订购信息。

3.1 功能方框图

图 3-1 显示器件的功能方框图。

GUID-3CFE0A3B-317D-48F1-9FA7-49317B9808B2-low.gif
由于引脚复用，所有外设引脚不能同时使用。
图 3-1 功能方框图

3.2 系统器件图

GUID-41F95423-8FD5-49CC-A40E-4D6EC3751544-low.gif图 3-2 外设块

4 Revision History

Changes from February 1, 2021 to May 30, 2021 (from Revision I (February 2021) to Revision J (May 2021))

  • 全局更改：将“仿真”更新/更改为“调试”Go
  • 添加了 Q1 器件型号Go
  • Updated/changed from "SCI" to "SCI/UART"Go
  • Updated/changed Device Compairson table footnote to show correct part numbersGo
  • Updated/changed the definition for VREGENZGo
  • Updated/changed oscillator footnoteGo
  • Updated/changed Security noteGo
  • Updated/changed Peripheral Frame informationGo
  • Added a row for Instaspin featureGo
  • Updated/changed image, Clock Tree, to remove WDCLK labelGo
  • Updated/changed "CPU Watchdog Module" to remove WDCLKGo
  • Added C2000 third-party search tool linkGo

5 Device Comparison

Table 5-1 lists the features of the TMS320F2806x devices.

Table 5-1 Device Comparison
FEATURE TYPE(1) 28069
28069-Q1
28069U(2)(5)
28069M(2)(3)
28069M-Q1
28069F(2)(3)
28069F-Q1
(90 MHz)		 28068U(2)(5)
28068M(2)(3)
28068F(2)(3)
(90 MHz)		 28067
28067-Q1
28067U(2)(5)
(90 MHz)		 28066
28066-Q1
28066U(2)(5)
(90 MHz)		 28065
28065-Q1
28065U(2)(5)
(90 MHz)		 28064
28064U(2)(5)
(90 MHz)		 28063
28063U(2)(5)
(90 MHz)		 28062
28062-Q1
28062U(2)(5)
28062F(2)(3)
28062F-Q1
(90 MHz)
Package Type
(PFP and PZP are PowerPAD HTQFPs.
PN and PZ are LQFPs.)		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP
Instruction cycle – 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns
Floating-Point Unit (FPU) Yes Yes Yes Yes Yes Yes Yes Yes
VCU Yes Yes No No Yes Yes No No
CLA 0 Yes No No No Yes No No No
6-Channel DMA 0 Yes Yes Yes Yes Yes Yes Yes Yes
On-chip Flash (16-bit word) – 128K 128K 128K 128K 64K 64K 64K 64K
On-chip SARAM (16-bit word) – 50K 50K 50K 34K 50K 50K 34K 26K
Code security for on-chip Flash, SARAM, and OTP blocks – Yes Yes Yes Yes Yes Yes Yes Yes
Boot ROM (32K × 16) – Yes Yes Yes Yes Yes Yes Yes Yes
One-time programmable (OTP) ROM
(16-bit word)		 – 1K 1K 1K 1K 1K 1K 1K 1K
ePWM channels 1 16 14 16 14 16 14 16 14 16 14 16 14 16 14 16 14
High-resolution ePWM Channels 1 8 8 8 8 8 8 8 8
eCAP inputs 0 3 3 3 3 3 3 3 3
HRCAP 0 4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1
eQEP modules 0 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
Watchdog timer – Yes Yes Yes Yes Yes Yes Yes Yes
12-Bit ADC MSPS 3 3.46 3.46 3.46 3.46 3.46 3.46 3.46 3.46
Conversion Time 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns
Channels 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12
Temperature Sensor Yes Yes Yes Yes Yes Yes Yes Yes
Dual Sample-and-Hold Yes Yes Yes Yes Yes Yes Yes Yes
32-Bit CPU timers – 3 3 3 3 3 3 3 3
Comparators with Integrated DACs 0 3 3 3 3 3 3 3 3
I2C 0 1 1 1 1 1 1 1 1
McBSP 1 1 1 1 1 1 1 1 1
eCAN 0 1 1 1 1 1 1 1 1
SPI 1 2 2 2 2 2 2 2 2
SCI/UART 0 2 2 2 2 2 2 2 2
USB 0 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2)
2-pin Oscillator 1 1 1 1 1 1 1 1
0-pin Oscillator 2 2 2 2 2 2 2 2
I/O pins (shared) GPIO – 54 40 54 40 54 40 54 40 54 40 54 40 54 40 54 40
AIO – 6 6 6 6 6 6 6 6
External interrupts – 3 3 3 3 3 3 3 3
Supply voltage (nominal) – 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Temperature options T: –40°C to 105°C – PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN
S: –40°C to 125°C – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP
Q: –40°C to 125°C(5)(4) – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.
(2) USB is present on TMS320F2806xU, TMS320F2806xM, and TMS320F2806xF devices.
(3) TMS320F2806xF devices are InstaSPIN-FOC™-enabled MCUs. TMS320F2806xM devices are InstaSPIN-MOTION™-enabled MCUs. But instaSPIN-MOTION is no longer recommended for new designs and will not have application support. For more information, see Section 10.3 for a list of InstaSPIN Technical Reference Manuals.
(4) The letter Q refers to AEC Q100 qualification for automotive applications.
(5) The Q temperature option is not available on the TMS320F2806xU devices.

5.1 Related Products

For information about similar products, see the following links:

TMS320F2802x Microcontrollers
The F2802x series offers the lowest pin-count and Flash memory size options. InstaSPIN-FOC™ versions are available.

TMS320F2803x Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the parallel control law accelerator (CLA) option.

TMS320F2805x Microcontrollers
The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs). InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.

TMS320F2806x Microcontrollers
The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the pin-count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-MOTION™ versions are available.

TMS320F2807x Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options. The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.

TMS320F28004x Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements. The F28004x series is the best roadmap option for those using the F2806x series. InstaSPIN-FOC and configurable logic block (CLB) versions are available.

6 Terminal Configuration and Functions

6.1 Pin Diagrams

Figure 6-1 shows the pin assignments on the 80-pin PN and PFP packages. Figure 6-2 shows the pin assignments on the 100-pin PZ and PZP packages.

GUID-5A6079D7-9643-4E79-9815-C0D442125487-low.gif
Pin 19: VREFHI and ADCINA0 share the same pin on the 80-pin PN and PFP devices and their use is mutually exclusive to one another. Pin 21: VREFLO is always connected to VSSA on the 80-pin PN and PFP devices.
The PowerPAD is not connected to the ground on the die. To facilitate effective heat dissipation, the PowerPAD must be connected to the ground plane of the PCB. It should not be left unconnected. For more details, see PowerPAD™ Thermally Enhanced Package.
Figure 6-1 80-Pin PN and PFP Packages (Top View)
GUID-E60ECA64-BCB3-4C29-8876-D8263A6470DD-low.gif
The PowerPAD is not connected to the ground on the die. To facilitate effective heat dissipation, the PowerPAD must be connected to the ground plane of the PCB. It should not be left unconnected. For more details, see PowerPAD™ Thermally Enhanced Package.
Figure 6-2 100-Pin PZ and PZP Packages (Top View)
Note:

The PowerPAD™ should be soldered to the ground (GND) plane of the PCB because this will provide the best thermal conduction path. For this device, the PowerPAD is not electrically shorted to the internal die VSS; therefore, the PowerPAD does not provide an electrical connection to the PCB ground. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be designed with this technology in mind. A thermal land is required on the surface of the PCB directly underneath the body of the PowerPAD. The thermal land should be soldered to the exposed lead frame die pad of the PowerPad package; the thermal land should be as large as needed to dissipate the required heat. An array of thermal vias should be used to connect the thermal pad to the internal GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details on using the PowerPAD package.

6.2 Signal Descriptions

Section 6.2.1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 5-1 for details. Inputs are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup (PU), which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do not have an internal pullup.

Note:

When the on-chip voltage regulator (VREG) is used, the GPIO19, GPIO26–27, and GPIO34–38 pins could glitch during power up. This potential glitch will finish before the boot mode pins are read and will not affect boot behavior. If glitching is unacceptable in an application, 1.8 V could be supplied externally. Alternatively, adding a current-limiting resistor (for example, 470 Ω) in series with these pins and any external driver could be considered to limit the potential for degradation to the pin and/or external circuitry. There is no power-sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered before the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins before or simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.

6.2.1 Signal Descriptions

PIN NAMEPIN NO.I/O/Z(1)DESCRIPTION
PZ
PZP		PN
PFP
JTAG
TRST1210IJTAG test reset with internal pulldown (PD). TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE:TRST is an active-high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application. (↓)
TCKSee GPIO38ISee GPIO38. JTAG test clock with internal pullup. (↑)
TMSSee GPIO36ISee GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (↑)
TDISee GPIO35ISee GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑)
TDOSee GPIO37O/ZSee GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.
(8-mA drive)
FLASH
VDD3VFL46373.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
TEST24536I/OTest Pin. Reserved for TI. Must be left unconnected.
CLOCK
XCLKOUTSee GPIO18O/ZSee GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
XCLKINSee GPIO19 and GPIO38ISee GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled through bit 14 in the CLKCTL register. If a crystal or resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register.
NOTE: Designs that use the GPIO38/XCLKIN/TCK pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device.
X16048IOn-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND.
X25947OOn-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected.
RESET
XRS119I/ODDevice Reset (in) and Watchdog Reset (out). These devices have a built-in power-on reset (POR) and brownout reset (BOR) circuitry. During a power-on or brownout condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3F FFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain device with an internal pullup. (↑) If this pin is driven by an external device, it should be done using an open-drain device.
ADC, COMPARATOR, ANALOG I/O
ADCINA716–IADC Group A, Channel 7 input
ADCINA61714IADC Group A, Channel 6 input
COMP3AIComparator Input 3A
AIO6I/ODigital AIO 6
ADCINA51815IADC Group A, Channel 5 input
ADCINA41916IADC Group A, Channel 4 input
COMP2AIComparator Input 2A
AIO4I/ODigital AIO 4
ADCINA320–IADC Group A, Channel 3 input
ADCINA22117IADC Group A, Channel 2 input
COMP1AIComparator Input 1A
AIO2I/ODigital AIO 2
ADCINA12218IADC Group A, Channel 1 input
ADCINA02319IADC Group A, Channel 0 input.
NOTE: VREFHI and ADCINA0 share the same pin on the 80-pin PN and PFP devices and their use is mutually exclusive to one another.
VREFHI2419ADC External Reference High – only used when in ADC external reference mode. See Section 8.9.2.1.
NOTE: VREFHI and ADCINA0 share the same pin on the 80-pin PN and PFP devices and their use is mutually exclusive to one another.
ADCINB735–IADC Group B, Channel 7 input
ADCINB63427IADC Group B, Channel 6 input
COMP3BIComparator Input 3B
AIO14I/ODigital AIO 14
ADCINB53326IADC Group B, Channel 5 input
ADCINB43225IADC Group B, Channel 4 input
COMP2BIComparator Input 2B
AIO12I/ODigital AIO12
ADCINB331–IADC Group B, Channel 3 input
ADCINB23024IADC Group B, Channel 2 input
COMP1BIComparator Input 1B
AIO10I/ODigital AIO 10
ADCINB12923IADC Group B, Channel 1 input
ADCINB02822IADC Group B, Channel 0 input
VREFLO2721ADC External Reference Low.
NOTE: VREFLO is always connected to VSSA on the 80-pin PN and PFP devices.
CPU AND I/O POWER
VDDA2520Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
VSSA2621Analog Ground Pin.
NOTE: VREFLO is always connected to VSSA on the 80-pin PN and PFP devices.
VDD32CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. Higher value capacitors may be used.
1412
3729
6351
8165
9172
VDDIO54Digital I/O Buffers Power Pin. Single supply source when VREG is enabled. Place a decoupling capacitor on each pin. The exact value should be determined by the system voltage regulation solution.
1311
3830
6149
7963
9374
VSS43Digital Ground Pins
1513
3628
4738
6250
8064
9273
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ9071IInternal voltage regulator (VREG) enable with internal pulldown. Tie directly to VSS (low) to enable the internal 1.8-V VREG. Tie directly to VDDIO (high) to disable the VREG and use an external 1.8-V supply.
GPIO AND PERIPHERAL SIGNALS(2)
GPIO08769I/O/ZGeneral-purpose input/output 0
EPWM1AOEnhanced PWM1 Output A and HRPWM channel
Reserved–Reserved
Reserved–Reserved
GPIO18668I/O/ZGeneral-purpose input/output 1
EPWM1BOEnhanced PWM1 Output B
Reserved–Reserved
COMP1OUTODirect output of Comparator 1
GPIO28467I/O/ZGeneral-purpose input/output 2
EPWM2AOEnhanced PWM2 Output A and HRPWM channel
Reserved–Reserved
Reserved–Reserved
GPIO38366I/O/ZGeneral-purpose input/output 3
EPWM2BOEnhanced PWM2 Output B
SPISOMIAI/OSPI-A slave out, master in
COMP2OUTODirect output of Comparator 2
GPIO497I/O/ZGeneral-purpose input/output 4
EPWM3AOEnhanced PWM3 output A and HRPWM channel
Reserved–Reserved
Reserved–Reserved
GPIO5108I/O/ZGeneral-purpose input/output 5
EPWM3BOEnhanced PWM3 output B
SPISIMOAI/OSPI-A slave in, master out
ECAP1I/OEnhanced Capture input/output 1
GPIO65846I/O/ZGeneral-purpose input/output 6
EPWM4AOEnhanced PWM4 output A and HRPWM channel
EPWMSYNCIIExternal ePWM sync pulse input
EPWMSYNCOOExternal ePWM sync pulse output
GPIO75745I/O/ZGeneral-purpose input/output 7
EPWM4BOEnhanced PWM4 output B
SCIRXDAISCI-A receive data
ECAP2I/OEnhanced Capture input/output 2
GPIO85443I/O/ZGeneral-purpose input/output 8
EPWM5AOEnhanced PWM5 output A and HRPWM channel
Reserved–Reserved
ADCSOCAOOADC start-of-conversion A
GPIO94939I/O/ZGeneral-purpose input/output 9
EPWM5BOEnhanced PWM5 output B
SCITXDBOSCI-B transmit data
ECAP3I/OEnhanced Capture input/output 3
GPIO107460I/O/ZGeneral-purpose input/output 10
EPWM6AOEnhanced PWM6 output A and HRPWM channel
Reserved–Reserved
ADCSOCBOOADC start-of-conversion B
GPIO117359I/O/ZGeneral-purpose input/output 11
EPWM6BOEnhanced PWM6 output B
SCIRXDBISCI-B receive data
ECAP1I/OEnhanced Capture input/output 1
GPIO124435I/O/ZGeneral-purpose input/output 12
TZ1ITrip Zone input 1
SCITXDAOSCI-A transmit data
SPISIMOBI/OSPI-B slave in, master out
GPIO139575I/O/ZGeneral-purpose input/output 13
TZ2ITrip Zone input 2
Reserved–Reserved
SPISOMIBI/OSPI-B slave out, master in
GPIO149676I/O/ZGeneral-purpose input/output 14
TZ3ITrip zone input 3
SCITXDBOSCI-B transmit data
SPICLKBI/OSPI-B clock input/output
GPIO158870I/O/ZGeneral-purpose input/output 15
ECAP2I/OEnhanced Capture input/output 2
SCIRXDBISCI-B receive data
SPISTEBI/OSPI-B slave transmit enable input/output
GPIO165544I/O/ZGeneral-purpose input/output 16
SPISIMOAI/OSPI-A slave in, master out
Reserved–Reserved
TZ2ITrip Zone input 2
GPIO175242I/O/ZGeneral-purpose input/output 17
SPISOMIAI/OSPI-A slave out, master in
Reserved–Reserved
TZ3ITrip zone input 3
GPIO185141I/O/ZGeneral-purpose input/output 18
SPICLKAI/OSPI-A clock input/output
SCITXDBOSCI-B transmit data
XCLKOUTO/ZOutput clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
GPIO196452I/O/ZGeneral-purpose input/output 19
XCLKINIExternal Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if it is being used for the other peripheral functions.
SPISTEAI/OSPI-A slave transmit enable input/output
SCIRXDBISCI-B receive data
ECAP1I/OEnhanced Capture input/output 1
GPIO2065I/O/ZGeneral-purpose input/output 20
EQEP1AIEnhanced QEP1 input A
MDXAOMcBSP transmit serial data
COMP1OUTODirect output of Comparator 1
GPIO2176I/O/ZGeneral-purpose input/output 21
EQEP1BIEnhanced QEP1 input B
MDRAIMcBSP receive serial data
COMP2OUTODirect output of Comparator 2
GPIO229878I/O/ZGeneral-purpose input/output 22
EQEP1SI/OEnhanced QEP1 strobe
MCLKXAI/OMcBSP transmit clock
SCITXDBOSCI-B transmit data
GPIO2321I/O/ZGeneral-purpose input/output 23
EQEP1II/OEnhanced QEP1 index
MFSXAI/OMcBSP transmit frame synch
SCIRXDBISCI-B receive data
GPIO249777I/O/ZGeneral-purpose input/output 24
ECAP1I/OEnhanced Capture input/output 1
EQEP2AIEnhanced QEP2 input A.
NOTE: eQEP2 is available only in the PZ and PZP packages.
SPISIMOBI/OSPI-B slave in, master out
GPIO253931I/O/ZGeneral-purpose input/output 25
ECAP2I/OEnhanced Capture input/output 2
EQEP2BIEnhanced QEP2 input B.
NOTE: eQEP2 is available only in the PZ and PZP packages.
SPISOMIBI/OSPI-B slave out, master in
GPIO267862I/O/ZGeneral-purpose input/output 26
ECAP3I/OEnhanced Capture input/output 3
EQEP2II/OEnhanced QEP2 index.
NOTE: eQEP2 is available only in the PZ and PZP packages.
SPICLKBI/OSPI-B clock input/output
USB0DP(3)I/OPositive Differential half of USB signal. To enable USB functionality on this pin, set the USBIOEN bit in the GPACTRL2 register.
GPIO277761I/O/ZGeneral-purpose input/output 27
HRCAP2IHigh-Resolution Input Capture 2
EQEP2SI/OEnhanced QEP2 strobe.
NOTE: eQEP2 is available only in the PZ and PZP packages.
SPISTEBI/OSPI-B slave transmit enable input/output
USB0DM(3)I/ONegative Differential half of USB signal. To enable USB functionality on this pin, set the USBIOEN bit in the GPACTRL2 register.
GPIO285040I/O/ZGeneral-purpose input/output 28
SCIRXDAISCI-A receive data
SDAAI/ODI2C data open-drain bidirectional port
TZ2ITrip zone input 2
GPIO294334I/O/ZGeneral-purpose input/output 29
SCITXDAOSCI-A transmit data
SCLAI/ODI2C clock open-drain bidirectional port
TZ3ITrip zone input 3
GPIO304133I/O/ZGeneral-purpose input/output 30
CANRXAICAN receive
EQEP2II/OEnhanced QEP2 index.
NOTE: eQEP2 is available only in the PZ and PZP packages.
EPWM7AOEnhanced PWM7 Output A and HRPWM channel
GPIO314032I/O/ZGeneral-purpose input/output 31
CANTXAOCAN transmit
EQEP2SI/OEnhanced QEP2 strobe.
NOTE: eQEP2 is available only in the PZ and PZP packages.
EPWM8AOEnhanced PWM8 Output A and HRPWM channel
GPIO329979I/O/ZGeneral-purpose input/output 32
SDAAI/ODI2C data open-drain bidirectional port
EPWMSYNCIIEnhanced PWM external sync pulse input
ADCSOCAOOADC start-of-conversion A
GPIO3310080I/O/ZGeneral-purpose input/output 33
SCLAI/ODI2C clock open-drain bidirectional port
EPWMSYNCOOEnhanced PWM external synch pulse output
ADCSOCBOOADC start-of-conversion B
GPIO346855I/O/ZGeneral-purpose input/output 34
COMP2OUTODirect output of Comparator 2
Reserved–Reserved
COMP3OUTODirect output of Comparator 3
GPIO357157I/O/ZGeneral-purpose input/output 35
TDIIJTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
Reserved–Reserved
Reserved–Reserved
Reserved–Reserved
GPIO367258I/O/ZGeneral-purpose input/output 36
TMSIJTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK.
Reserved–Reserved
Reserved–Reserved
Reserved–Reserved
GPIO377056I/O/ZGeneral-purpose input/output 37
TDOO/ZJTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive).
Reserved–Reserved
Reserved–Reserved
Reserved–Reserved
GPIO386754I/O/ZGeneral-purpose input/output 38
XCLKINIExternal Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if it is being used for the other functions.
TCKIJTAG test clock with internal pullup
Reserved–Reserved
Reserved–Reserved
Reserved–Reserved
GPIO396653I/O/ZGeneral-purpose input/output 39
Reserved–Reserved
Reserved–Reserved
Reserved–Reserved
GPIO4082–I/O/ZGeneral-purpose input/output 40
EPWM7AOEnhanced PWM7 output A and HRPWM channel
SCITXDBOSCI-B transmit data
Reserved–Reserved
GPIO4176–I/O/ZGeneral-purpose input/output 41
EPWM7BOEnhanced PWM7 output B
SCIRXDBISCI-B receive data
Reserved–Reserved
GPIO421–I/O/ZGeneral-purpose input/output 42
EPWM8AOEnhanced PWM8 output A and HRPWM channel
TZ1ITrip zone input 1
COMP1OUTODirect output of Comparator 1
GPIO438–I/O/ZGeneral-purpose input/output 43
EPWM8BOEnhanced PWM8 output B
TZ2ITrip zone input 2
COMP2OUTODirect output of Comparator 2
GPIO4456–I/O/ZGeneral-purpose input/output 44
MFSRAI/OMcBSP receive frame synch
SCIRXDBISCI-B receive data
EPWM7BOEnhanced PWM7 output B
GPIO5042–I/O/ZGeneral-purpose input/output 50
EQEP1AIEnhanced QEP1 input A
MDXAOMcBSP transmit serial data
TZ1ITrip zone input 1
GPIO5148–I/O/ZGeneral-purpose input/output 51
EQEP1BIEnhanced QEP1 input B
MDRAIMcBSP receive serial data
TZ2ITrip zone input 2
GPIO5253–I/O/ZGeneral-purpose input/output 52
EQEP1SI/OEnhanced QEP1 strobe
MCLKXAI/OMcBSP transmit clock
TZ3ITrip zone input 3
GPIO5365–I/O/ZGeneral-purpose input/output 53
EQEP1II/OEnhanced QEP1 index
MFSXAI/OMcBSP transmit frame synch
Reserved–Reserved
GPIO5469–I/O/ZGeneral-purpose input/output 54
SPISIMOAI/OSPI-A slave in, master out
EQEP2AIEnhanced QEP2 input A
HRCAP1IHigh-Resolution Input Capture 1
GPIO5575–I/O/ZGeneral-purpose input/output 55
SPISOMIAI/OSPI-A slave out, master in
EQEP2BIEnhanced QEP2 input B
HRCAP2IHigh-Resolution Input Capture 2
GPIO5685–I/O/ZGeneral-purpose input/output 56
SPICLKAI/OSPI-A clock input/output
EQEP2II/OEnhanced QEP2 index
HRCAP3IHigh-Resolution Input Capture 3
GPIO5789–I/O/ZGeneral-purpose input/output 57
SPISTEAI/OSPI-A slave transmit enable input/output
EQEP2SI/OEnhanced QEP2 strobe
HRCAP4IHigh-Resolution Input Capture 4
GPIO5894–I/O/ZGeneral-purpose input/output 58
MCLKRAI/OMcBSP receive clock
SCITXDBOSCI-B transmit data
EPWM7AOEnhanced PWM7 output A and HRPWM channel
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal. See the Systems Control and Interrupts chapter of the TMS320x2806x Technical Reference Manual .
(3) Depending on your USB application, additional pins may be required to maintain compliance with the USB 2.0 Specification. For more information, see the Universal Serial Bus (USB) Controller chapter of the TMS320x2806x Technical Reference Manual .

7 Specifications

 
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