4 示例

下面提供了两个示例，用于说明在 48KHz 的采样频率下如何为两个不同的目标应用配置 AGC。示例 1 适用于噪声远低于输入信号的情况。示例 2 适用于噪声明显大于所需信号的情况。

示例 1：当噪声的振幅明显小于信号的振幅时，AGC 可以通过将噪声阈值设置为高于本底噪声但低于可能的最弱信号来轻松区分噪声和信号。当可以进行这种清晰的区分时，可以使用更高的最大增益，因为增加噪声的可能性很小。以下值可用于该应用。

• 目标电平 = -36dB
• 最大增益 = 24dB
• 噪声阈值 = -85dB
• 起音时间 = 0.1ms
• 释放时间 = 20ms
• 起音保持 = 0.0417ms
• 释放保持 = 20ms
• 起音迟滞 = 1dB
• 释放迟滞 = 3dB
• 噪声迟滞 = 4dB

# Key: w 9C XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
#               # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device.Note that there are 
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 2-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies 
# Wait for 1ms.
#
w 9C 00 00 # Goto Page 0
w 9C 02 81 # Wake-up device by I2C write into P0_R2 using internal AREG
w 9C 02 81 # Exit Sleep mode
d 10       # Wait for 16 ms
w 9c 6C 4C # Enable AGC in DSP_CFG1 and Override AGC parameters with user values
w 9C 3C 01 # Select AGC on Ch. 1 using CH1_CFG0
w 9C 41 01 # Select AGC on Ch. 2 using CH2_CFG0
w 9C 70 E7 # AGC LVL = -36 dB, AGC GAIN = 24 dB
w 9C 00 05          # Goto Page 5
w 9C 7C 7F B5 16 50 # AGC Release Time Alpha 
w 9C 00 05          # Goto Page 6
w 9C 08 00 4A E9 B0 # AGC Release Time Beta  
w 9C 0C 50 FC 64 5C # AGC Attack Time Alpha 
w 9C 10 2F 03 9B A4 # AGC Attack Time Beta 
w 9C 18 00 00 02 00 # AGC Attack Debounce 
w 9C 1C 00 04 B0 00 # AGC Release Debounce 
w 9C 20 FF FF AB 00 # AGC Noise Threshold : -85 dB 
w 9C 44 00 04 B0 00 # AGC Noise Debounce 
w 9C 3C 00 00 01 00 # AGC Attack Hysteresis 
w 9C 34 00 00 03 00 # AGC Release Hysteresis
w 9C 54 00 00 04 00 # AGC Noise Hysteresis : 4 dB
w 9C 78 7F 7F D2 B4 # AGC HPF B0 
w 9c 7C 80 80 2D 4C # AGC HPF B1 
w 9C 00 06          # Goto Page 6
w 9c 54 7E FF A5 68 # AGC HPF A1 
 
w 9C 00 00 # Goto Page 0
w 9c 07 30 # TDM Mode with 32 Bits/Channel
w 9C 73 C0 # Enable Ch.1 - Ch.2
w 9C 74 C0 # Enable ASI Output channels
w 9c 75 E0 # Power up ADC

示例 2：当噪声非常高且不易与微弱信号区分开来时，不建议使用较高的最大增益。必须将噪声阈值设置为更接近预期的本底噪声。以下值可用于该应用。

• 目标电平 = -36dB
• 最大增益 = 18dB
• 噪声阈值 = -80dB
• 起音时间 = 0.1ms
• 释放时间 = 20ms
• 起音保持 = 0.0417ms
• 释放保持 = 20ms
• 起音迟滞 = 1dB
• 释放迟滞 = 3dB
• 噪声迟滞 = 4dB

# Key: w 9C XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
#               # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device.Note that there are 
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 2-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies 
# Wait for 1ms.
#
w 9C 00 00 # Goto Page 0
w 9C 02 81 # Wake-up device by I2C write into P0_R2 using internal AREG
w 9C 02 81 # Exit Sleep mode
d 10       # Wait for 16 ms
w 9c 6C 4C # Enable AGC in DSP_CFG1 and Override AGC parameters with user values
w 9C 3C 01 # Select AGC on Ch. 1 using CH1_CFG0
w 9C 41 01 # Select AGC on Ch. 2 using CH2_CFG0
w 9C 70 E5 # AGC LVL = -36 dB, AGC GAIN = 18 dB
w 9C 00 05          # Goto Page 5
w 9C 7C 7F B5 16 50 # AGC Release Time Alpha 
w 9C 00 05          # Goto Page 6
w 9C 08 00 4A E9 B0 # AGC Release Time Beta  
w 9C 0C 50 FC 64 5C # AGC Attack Time Alpha 
w 9C 10 2F 03 9B A4 # AGC Attack Time Beta 
w 9C 18 00 00 02 00 # AGC Attack Debounce 
w 9C 1C 00 04 B0 00 # AGC Release Debounce 
w 9C 20 FF FF B0 00 # AGC Noise Threshold : -80 dB
w 9C 44 00 04 B0 00 # AGC Noise Debounce 
w 9C 3C 00 00 01 00 # AGC Attack Hysteresis 
w 9C 34 00 00 03 00 # AGC Release Hysteresis
w 9C 54 00 00 04 00 # AGC Noise Hysteresis : 4 dB
w 9C 78 7F 7F D2 B4 # AGC HPF B0 
w 9C 7C 80 80 2D 4C # AGC HPF B1 
w 9C 00 06          # Goto Page 6
w 9C 54 7E FF A5 68 # AGC HPF A1 
 
w 9C 00 00 # Goto Page 0
w 9C 07 30 # TDM Mode with 32 Bits/Channel
w 9C 73 c0 # Enable Ch.1 - Ch.2 
w 9C 74 c0 # Enable ASI Output channels
w 9C 75 e0 # Power up ADC