SWRZ119 February   2022 CC1311R3

 

  1.   Trademarks
  2. 1Advisories Matrix
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Advisories
    1.     Radio_01
    2.     Power_03
    3.     I2C_01
    4.     I2S_01
    5.     CPU_01
    6.     CPU_02
    7.     CPU_Sys_01
    8.     Sys_01
    9. 3.1 Sys_05
    10.     SYSCTRL_01
    11.     IOC_01
    12.     ADC_01
    13.     ADC_02
    14.     ADC_03
  5. 4Revision History

Advisories Matrix

Table 1-1 lists all advisories, modules affected, and the applicable silicon revisions.

Table 1-1 Advisories Matrix
MODULE DESCRIPTION SILICON REVISIONS AFFECTED
B
Radio Advisory Radio_01 — Proprietary radio modes: spurious emissions can affect regulatory compliance Yes
Power Advisory Power_03 — Increased voltage ripple at low supply voltages when DC/DC converter is enabled Yes
I2C Advisory I2C_01 — I2C module master status bit is set late Yes
I2S Advisory I2S_01 — I2S bus faults are not reported Yes
CPU Advisory CPU_01Arm® Errata #838869: Store immediate overlapping exception return operation might vector to incorrect interrupt Yes
CPU Advisory CPU_02Arm® Errata #752770: Interrupted loads to SP can cause erroneous behavior Yes
CPU, System Advisory CPU_Sys_01 — The SysTick calibration value (register field CPU_SCS.STCR.TENMS) used to set up 10-ms periodic ticks is incorrect when the system CPU is running off divided down 48-MHz clock Yes
System Advisory Sys_01 — Device might boot into ROM serial bootloader when waking up from shutdown Yes
System Advisory Sys_05 — Elevated power-on-reset (POR) threshold voltage at low temperatures Yes
System Controller Advisory SYSCTRL_01 — Resets occurring in a specific 2-MHz period during initial power up are incorrectly reported Yes
ADC Advisory ADC_01 — Periodic ADC trigger at 200 kHz rate can be ignored when XOSC_HF is turned on or off Yes
ADC Advisory ADC_02 — ADC samples can be delayed by 2 or 14 clock cycles (24 MHz) when XOSC_HF is turned on or off, resulting in sample jitter Yes
ADC Advisory ADC_03 — Software can hang when reading the ADC FIFO if a single manual ADC trigger is generated immediately after the ADC is enabled Yes