SWRZ118 February   2022 CC1311P3

 

  1.   Trademarks
  2. 1Advisories Matrix
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Advisories
    1.     Radio_01
    2.     Radio_02
    3.     Power_03
    4.     I2C_01
    5.     I2S_01
    6.     CPU_01
    7.     CPU_02
    8.     CPU_Sys_01
    9.     Sys_01
    10. 3.1 Sys_05
    11.     SYSCTRL_01
    12.     ADC_01
    13.     ADC_02
    14.     ADC_03
  5. 4Revision History

ADC_03

Software can hang when reading the ADC FIFO if a single manual ADC trigger is generated immediately after the ADC is enabled

Revisions Affected:

Revision B

Details:

There is no dedicated clock source selection for the ADC clock. The clock is derived from either XOSC_HF or RCOSC_HF, but defaults to XOSC_HF-derived clock whenever this is turned on.

When the ADC clock source is switched from RCOSC_HF to XOSC_HF-derived clock, the clock will stop for 2 cycles (24 MHz).

When the ADC clock source is switched from XOSC_HF-derived clock to RCOSC_HF-derived clock, the clock will stop for additionally 12 clock cycles, as the RCOSC_HF-derived clock is not ready when switch is done.

The additional 12 clock cycles introduces a race between trigger-event and ADC trigger-detector to get out of reset.

Workaround 1:

TI software adds a short delay at the end of the function that enables the ADC. Use SimpleLink CC13xx and CC26xx SDK 5.40 or later

Workaround 2:

Ensure that XOSC_HF is not turned on or off while the ADC is used.