Revision(s) Affected:

IWR1642 ES1.0 and IWR1642 ES2.0

Description:

During the 3.3-V supply ramp, the GPIO outputs could possibly see a short glitch (rising above the 0 V for a short duration), if the 3.3V supply powers up before the 1.8V supply. This GPIO glitch cannot be avoided by just a pulldown resistor. If the GPIO glitch during boot-up is high enough, it could be falsely detected as a “high”.

Workaround(s):

Powering up the 1.8V supply before the 3.3V supply resolved the issue. Incase that is not feasible, AND the GPIO is used for critical controls where glitch cannot be tolerated, the GPIO output should be gated by the nRESET signal of the xWR device.

Using a tri-state buffer (for example: SN74LVC1G126-Q1) externally to isolate the GPIO output from the system until the nRESET of xWR device is released. At this point, all the supplies are expected to be stable.