SWRZ071D May   2017  – December 2020 AWR1243

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Advisory to Silicon Variant / Revision Map
  5. 5Known Design Exceptions to Functional Specifications
    1.     MSS#06
    2.     MSS#18
    3.     MSS#44
    4.     ANA#01
    5.     ANA#02
    6.     ANA#03
    7.     ANA#04
    8.     ANA#06
    9.     ANA#07
    10.     ANA#08A
    11.     ANA#09A
    12.     ANA#10A
    13.     ANA#11A
    14.     ANA#12A
    15.     ANA#13
    16.     ANA#15
    17.     ANA#17A
    18.     ANA#18B
    19.     ANA#20
    20.     ANA#21A
    21.     ANA#22A
    22.     ANA#23
    23.     ANA#24A
    24.     ANA#27
  6. 6Trademarks
    1.     Revision History

ANA#20

Occasional Failures Observed During Calibration of the Radar Subsystem

Revision(s) Affected:

AWR1243 ES1.0, AWR1243 ES2.0, and AWR1243 ES3.0

Description:

Rare occurrences of failures have been observed in the Dual-Clock Comparator (DCC) module, as a result the APLL or Synthesizer may report a failure.

Workaround(s):

Workaround #1:

Any APLL calibration failure needs to be responded with a reset cycle.

or

Workaround #2:

Any SYNTH calibration failure reported by the BSS will require an RFinit.