SWRA574B October   2017  – February 2020 AWR1243 , AWR2243

 

  1.   AWR2243 Cascade
    1.     Trademarks
    2. 1 Cascaded AWR2243 System
    3. 2 Synchronization of AWR2243 Chips
      1. 2.1 20 GHz (FMCW) RF LO Sync
      2. 2.2 Digital Frame Sync
        1. 2.2.1 Frame (Burst) and Chirp Timing in AWR2243
        2. 2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System
        3. 2.2.3 Inter Chip Imbalance of Digital Sync Timing
      3. 2.3 40 MHz (System) Reference Clock Synchronization
    4. 3 Connectivity
      1. 3.1 20 GHz LO Sync Pins Connectivity
      2. 3.2 DIG_SYNC Connectivity
      3. 3.3 40 MHz (System) Reference Clock Connectivity
    5. 4 20 GHz LO Sync Link Budget
    6. 5 Software Messaging
      1. 5.1 Configuration of Devices
      2. 5.2 Configuration of Frames
        1. 5.2.1 Similar Configuration Across AWR2243 Devices
        2. 5.2.2 Dissimilar Configuration Across AWR2243 Devices
      3. 5.3 Triggering of Frames
      4. 5.4 Example Usage
      5. 5.5 Other Usages
    7. 6 Advantages of AWR2243 Cascading System
    8. 7 References
  2.   Revision History

2 Synchronization of AWR2243 Chips

In a cascaded system, there is one Master chip and one or many Slave chips. These cascaded devices are synchronized using the following interfaces:

  • 20 GHz (FMCW) RF LO synchronization
  • Digital frame timing synchronization
  • 40 MHz (System) reference clock synchronization

The 20 GHz (FMCW) RF LO is generated by the master chip and distributed to the slaves and the master. The relevant signals/pins are referred to as FM_CW_SYNCx/CLKx or 20 GHz LO in this document.

The frame timing synchronization is controlled by either the master chip, in the case of software message based frame trigger, or by the host processor, in the case of hardware based frame trigger. The relevant signals/pins are referred to as SYNC_IN/OUT or DIG_SYNC_IN/OUT in this document.

The 40 MHz system clock may be generated by either the master chip or externally supplied. The relevant pins are OSC_CLKOUT, CLKP and CLKM.

Detailed description on syncing is given in the following sections.