SWRA574B October   2017  – February 2020 AWR1243 , AWR2243

 

  1.   AWR2243 Cascade
    1.     Trademarks
    2. 1 Cascaded AWR2243 System
    3. 2 Synchronization of AWR2243 Chips
      1. 2.1 20 GHz (FMCW) RF LO Sync
      2. 2.2 Digital Frame Sync
        1. 2.2.1 Frame (Burst) and Chirp Timing in AWR2243
        2. 2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System
        3. 2.2.3 Inter Chip Imbalance of Digital Sync Timing
      3. 2.3 40 MHz (System) Reference Clock Synchronization
    4. 3 Connectivity
      1. 3.1 20 GHz LO Sync Pins Connectivity
      2. 3.2 DIG_SYNC Connectivity
      3. 3.3 40 MHz (System) Reference Clock Connectivity
    5. 4 20 GHz LO Sync Link Budget
    6. 5 Software Messaging
      1. 5.1 Configuration of Devices
      2. 5.2 Configuration of Frames
        1. 5.2.1 Similar Configuration Across AWR2243 Devices
        2. 5.2.2 Dissimilar Configuration Across AWR2243 Devices
      3. 5.3 Triggering of Frames
      4. 5.4 Example Usage
      5. 5.5 Other Usages
    7. 6 Advantages of AWR2243 Cascading System
    8. 7 References
  2.   Revision History

2.2.3 Inter Chip Imbalance of Digital Sync Timing

Ideally, the DIG_SYNC_IN (shown as Dig Sync in Figure 6) reaching the relevant circuits in all chips is balanced in delay, resulting in perfect timing synchronization of chirps. But practically, there are delay imbalances across different AWR2243 devices in a cascaded system. Most of this delay imbalance is due to manufacturing process variation among the AWR2243 devices. Some delay imbalance is due to temperature differences across the devices. Further there is a one clock uncertainty in the synchronizer circuit in each device for each occurrence of the DIG_SYNC_IN pulse. These imbalances are summarized in Table 1.

Table 1. DIG_SYNC_IN Imbalance Summary

DIG_SYNC_IN Inter-Chip Imbalance Type Total Inter-Chip Imbalance Magnitude
Imbalances due to chip process + voltage differences in a given cascade board Up to 4 ns approximately
Imbalances due to chip temperature differences in a given cascade board (up to 40°C) Up to 0.6 ns approximately
Imbalances due to synchronization uncertainty Either 0 or 0.55 ns (1)
  1. This is variable on each occurrence of the DIG_SYNC_IN pulse. The numbers provided assume that the ADC is operated in regular mode. In low power operation these numbers should be doubled due to the ADC clock frequency being half of the regular mode.