SPVA065 June   2026 TIC12400-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2On-Chip ADC Front-End Architecture Overview
  6. 3Understanding the ILKG Specification in the Datasheet
    1. 3.1 Interpretation of the ±110 µA Specification
    2. 3.2 The Leakage Current Is MUX-Activated and Time-Limited
  7. 4Design Considerations with Weak Voltage Sources
    1. 4.1 Definition of a Weak Voltage Source
    2. 4.2 Mechanism of the Sampling Spike
  8. 5Quantitative Model and Error Estimation
    1. 5.1 Voltage Step During the Sampling Window
    2. 5.2 Steady-State Offset with High-Impedance Sources
  9. 6Design Mitigation Methods
    1. 6.1 Method 1: Strengthen the Voltage Source
    2. 6.2 Method 2: External RC Compensation (Recommended)
    3. 6.3 Method 3: Static Offset Calibration
  10. 7Summary
  11. 8References

The Leakage Current Is MUX-Activated and Time-Limited

Bench measurements demonstrate that the ILKG current is not continuously present on the INx pin. Instead, it is injected only when the internal MUX actively connects a specific INx channel to the ADC or comparator circuitry. This transient lasts for the duration of the configured sampling window—approximately Tadc when the channel is assigned to ADC mode, or approximately Tcomp when assigned to comparator mode. Outside of these windows, the INx pin is electrically isolated from the internal ADC front-end.

Figure 3-1 and Figure 3-2 show oscilloscope captures of the INx pin voltage during the sampling window in ADC mode and comparator mode, respectively. In both cases, the wetting current is set to 0 mA, and the voltage excursion at the INx pin is caused entirely by the transient MUX-connection current charging the external and parasitic capacitance on the INx node. Critically, switching between ADC and comparator configuration changes only the pulse width of the observed voltage spike, not its amplitude, which confirms that this phenomenon is associated with the MUX and internal ADC circuitry rather than with any external wetting current source.

 INx Pin Voltage During Sampling Window: ADC Mode Figure 3-1 INx Pin Voltage During Sampling Window: ADC Mode
  INx Pin Voltage During Sampling Window: Comparator Mode Figure 3-2 INx Pin Voltage During Sampling Window: Comparator Mode