SPRZ423J October   2014  – March 2023 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076

 

  1.   Abstract
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision C Usage Notes and Advisories
    1. 3.1 Silicon Revision C Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 SYS/BIOS: Version Implemented in Device ROM is not Maintained
      4. 3.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions
      5. 3.1.5 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY Bit is in its Ready State (1)
    2. 3.2 Silicon Revision C Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
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      30.      Advisory
      31.      Advisory
      32.      Advisory
      33.      Advisory
      34.      Advisory
  5. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
  6. 5Documentation Support
  7. 6Trademarks
  8. 7Revision History

1.2 Advisories Matrix

Table 1-2 Advisories Matrix
MODULE DESCRIPTION SILICON REVISIONS AFFECTED
B C
Analog Bandgap References Yes Yes
Analog Trim of Some TMX Devices Yes
ADC ADC: ADC Post-Processing Block Limit Compare Yes Yes
ADC ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes Yes
ADC ADC: DMA Read of Stale Result Yes Yes
ADC ADC: Random Conversion Errors Yes
ADC ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule Yes
ADC ADC: 12-Bit Switch Resistance Yes
ADC ADC: 12-Bit Input Capacitance When Switching Channel Groups Yes
XRS may Toggle During Power Up Yes
CLB CLB: Back-to-Back PUSH or PULL Instructions With More Than One Active High-Level Controller (HLC) Channel is Not Supported Yes Yes
USB USB: USB DMA Event Triggers are not Supported Yes Yes
VREG VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ Yes
Flash Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR Yes Yes
Flash Flash: Minimum Programming Word Size Yes Yes
ePIE ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled Yes
eQEP eQEP: Position Counter Incorrectly Reset on Direction Change During Index Yes Yes
eQEP eQEP: eQEP Inputs in GPIO Asynchronous Mode Yes Yes
PLL PLL: May Not Lock on the First Lock Attempt Yes Yes
PLL PLL: Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective Yes Yes
SDFM SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and OSR = 256 Yes Yes
SDFM SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and Enabled for the First Time Yes Yes
SDFM SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using PWM FILRES Signal Yes Yes
SDFM SDFM: Comparator Filter Module may Generate Spurious Over-Value and Under-Value Conditions Yes Yes
SDFM SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR Settings Will Trigger Spurious Comparator Events Yes Yes
SDFM SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR) Will Trigger Spurious Data Acknowledge Events Yes Yes
SDFM SDFM: Manchester Mode (Mode 2) Does Not Produce Correct Filter Results Under Several Conditions Yes Yes
FPU FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation Yes Yes
FPU FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions Yes Yes
Memory Memory: Prefetching Beyond Valid Memory Yes Yes
INTOSC INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift Yes Yes
Low-Power Modes Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity Yes Yes
I2C I2C: SDA and SCL Open-Drain Output Buffer Issue Yes Yes
ePWM ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window Yes Yes
ePWM ePWM: ePWM Dead-Band Delay Value Cannot be Set to 0 When Using Shadow Load Mode for RED/FED Yes Yes
ePWM ePWM: Trip Events Will Not be Filtered by the Blanking Window for the First 3 Cycles After the Start of a Blanking Window Yes Yes
SYSTEM SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang Yes Yes
CMPSS CMPSS: COMPxLATCH May Not Clear Properly Under Certain Conditions Yes Yes
CMPSS CMPSS: Ramp Generator May Not Start Under Certain Conditions Yes Yes
GPIO GPIO: Open-Drain Configuration May Drive a Short High Pulse Yes Yes
During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer Yes Yes
Boot ROM Boot ROM: Calling SCI Bootloader from Application Yes Yes
Boot ROM Boot ROM: Device Will Hang During Boot if X1 Clock Source is not Present Yes