SPRUIY9C May   2021  – December 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
  6. 2Hardware
    1. 2.1 EVM Revisions and Assembly Variants
    2. 2.2 Important Usage Notes
    3. 2.3 System Description
      1. 2.3.1 Functional Block Diagram
      2. 2.3.2 Power-On/Off Procedures
        1. 2.3.2.1 Power-On Procedure
        2. 2.3.2.2 Power-Off Procedure
      3. 2.3.3 Peripheral and Major Component Description
        1. 2.3.3.1  Clocking
          1. 2.3.3.1.1 Ethernet PHY Clock
          2. 2.3.3.1.2 AM64x SoC Clock
        2. 2.3.3.2  Reset
        3. 2.3.3.3  Power
          1. 2.3.3.3.1 Power Input
          2. 2.3.3.3.2 USB Type-C Interface for Power Input
          3. 2.3.3.3.3 Power Fault Indication
          4. 2.3.3.3.4 Power Supply
          5. 2.3.3.3.5 Power Sequencing
          6. 2.3.3.3.6 Power Supply
        4. 2.3.3.4  Configuration
          1. 2.3.3.4.1 Boot Modes
        5. 2.3.3.5  JTAG
        6. 2.3.3.6  Test Automation
        7. 2.3.3.7  UART Interface
        8. 2.3.3.8  Memory Interfaces
          1. 2.3.3.8.1 LPDDR4 Interface
          2. 2.3.3.8.2 MMC Interface
            1. 2.3.3.8.2.1 Micro SD Interface
            2. 2.3.3.8.2.2 WiLink Interface
            3. 2.3.3.8.2.3 OSPI Interface
            4. 2.3.3.8.2.4 Board ID EEPROM Interface
        9. 2.3.3.9  Ethernet Interface
          1. 2.3.3.9.1 DP83867 PHY Default Configuration
          2. 2.3.3.9.2 DP83867 – Power, Clock, Reset, Interrupt and LEDs
          3. 2.3.3.9.3 Industrial Application LEDs
        10. 2.3.3.10 USB 3.0 Interface
        11. 2.3.3.11 PRU Connector
        12. 2.3.3.12 User Expansion Connector
        13. 2.3.3.13 MCU Connector
        14. 2.3.3.14 Interrupt
        15. 2.3.3.15 I2C Interface
        16. 2.3.3.16 IO Expander (GPIOs)
  7. 3Hardware Design Files
  8. 4Compliance Information
    1. 4.1 Regulatory Compliance
  9. 5Additional Information
    1. 5.1 Known Issues
      1. 5.1.1 Issue 1: LP8733x Max output Capacitance Spec Exceeded on LDO0 and LDO1
      2. 5.1.2 Issue 2: LP8733x Output Voltage of 0.9V Exceeds AM64x VDDR_CORE max Voltage Spec of 0.895 V
      3. 5.1.3 Issue 3 - SDIO Devices on MMC0 Require Careful Trace Lengths to Meet Interface Timing Requirements
      4. 5.1.4 Issue 4 - LPDDR4 Data Rate Limitation in Stressful Conditions
      5. 5.1.5 Issue 5 - Junk Character
      6. 5.1.6 Issue 6 - Test Power Down Signal Floating
      7. 5.1.7 Issue 7 - uSD Boot Not Working
    2.     Trademarks
    3.     65
  10. 6Revision History
2.3.3.8.2.4 Board ID EEPROM Interface

The AM64x processor is identified by the version and serial number, which are stored in the onboard EEPROM. The Board ID memory shall be configured to respond to address 0x51. AT24C512C-MAHM-T from Microchip is used, this is interfaced to I2C0 port of the SOC. I2C address of the EEPROM can be modified by driving the A0, A1, A2 pins to LOW. The write-protect input, when connected to GND, allows normal write operations. When the WP pin is connected directly to VCC, all write operations to the protected memory are inhibited. If the pin is left floating, then the WP pin is internally pulled down to GND. Here, WP is connected through GND through 10k resistor.

SK-AM64 SK-AM64B Board ID EEPROM Figure 2-18 Board ID EEPROM