SPRUI03D July 2015 – January 2022
Several instructions in the C6600 instruction set support a 128-bit register operand which can be specified as a register quad.
A register quad should be specified on the A side or the B side, depending on which functional unit an instruction is to be executed on, and whether a cross functional unit data path is utilized by the instruction. You cannot mix A-side and B-side registers in the same register quad operand.
The general syntax for a register quad is as follows, where (n%4 == 0):
Rn+3:Rn+2:Rn+1:Rn | or | Rn+3::Rn |
The legal register quads are:
A Register Quads | Short Form | B Register Quads | Short Form |
---|---|---|---|
A3:A2:A1:A0 | A3::A0 | B3:B2:B1:B0 | B3::B0 |
A7:A6:A5:A4 | A7::A4 | B7:B6:B5:B4 | B7::B4 |
A11:A10:A9:A8 | A11::A8 | B11:B10:B9:B8 | B11::B8 |
A15:A14:A13:A12 | A15::A12 | B15:B14:B13:B12 | B15::B12 |
A19:A18:A17:A16 | A19::A16 | B19:B18:B17:B16 | B19::B16 |
A23:A22:A21:A20 | A23::A20 | B23:B22:B21:B20 | B23::B20 |
A27:A26:A25:A24 | A27::A24 | B27:B26:B25:B24 | B27::B24 |
A31:A30:A29:A28 | A31::A28 | B31:B30:B29:B28 | B31::B28 |
Here is an example of an ADD instruction that uses register quad operands:
QMPYSP .M1 A27:A26:A25:A24, A11:A10:A9:A8, A19:A18:A17:A16
For details on using register quads in C6600 linear assembly, see the TMS320C6000 Optimizing Compiler User's Guide.
For more information on functional units, including which assembly instructions require which functional type, see the TMS320C66x CPU and Instruction Set Reference Guide.