1 Introduction

There are multiple boot modes supported by J7 SoC, mainly can be divided into two types: peripheral booting and memory booting. Different boot mode required different hardware design and software configuration, details can be found in boot mode setting.

• For peripheral booting, the ROM code gets the image through selected communication interface to run the silicon. This is normally used in development phase.

• For memory booting, the ROM code gets the image from memory devices, such as flash, SD Card, EMMC, to run the silicon. This is normally used in final product.

There is another special boot mode called “No boot” mode which is used for JTAG connection to directly load the image to DDR through JTAG interface during development phases.

For J7 based design, OSPI boot mode is normally chosen because of boot speed. Then, how to flash the OSPI flash during development and manufacturing is an important part of the design process. Different projects use different hardware design, and bring different interface. Even under the same hardware design, different silicon type will also bring different restrictions. So one flashing solution cannot be used to deal with all cases, this note introduces the OSPI flashing solution in HS silicon with different hardware design.

As shown in Figure 1-1, from security enabled product perspective, three phases included in J7 SOC development. In each phase, different device types have different features and are used for different purposes.

GP silicon is the basic silicon without security features enabled, on GP silicon, JTAG is enabled and then it can be used for flashing, meanwhile all the system binary does not need to be signed and encrypted, so GP silicon normally used for functionality development.

HS-FS is Field Securable silicon with valid secure features, but not enabled until the customer keys are programmed during manufacture. The Device Management and Security Control (DMSC) subsystem is protected by TI security keys. On HS-FS silicon, the JTAG can still be used for flashing.

HS-SE is Security Enforced silicon with customer keys programmed. This is done with the Key writer tools provided by TI at customer site. Therefore, the image running on the silicon need to be signed and encrypted by the keys and JTAG is disabled by default to enforce the security. On HS-SE silicon, separate consideration required for flashing.

According to the system design, different flashing solution can be chosen. The solution can follow the flowchart shown in Figure 1-2.

How to select the proper flashing solution depends on the system design.

• Uniflash can be used when there is UART interface available. This is the simpler solution, but the UART interface in final product may introduce additional cost and exposure of system information in the UART log. Also, the device can only be flashing online in factory, lack of flexibility and efficiency, and the UART is slower speed interface and not suitable for flashing large binaries.

As shown in above flow chart, secondary boot mode like SD boot mode is required to do the flashing when UART interface is not available. This requires switching to the secondary memory boot mode that may:

• Need separate interface in the design. The procedure is simple and flexible, but also introduce the additional hardware cost and low efficiency in factory.
• Separate consideration required for OSPI-memory-only boot mode. It is the most cost-effective design as no additional hardware required, and improved factory efficiency because it can be flashing offline. There is a big challenge for this solution: how to support the offline flashing and then how to do online flashing after the board is converted to SE device. A new method is proposed in this application notes to support this scenario.

All the HS flashing solution were tested in SDK7.1 software with J721E-EVM hardware and works fine.