SPRAC31 February   2019 TMS320C5505 , TMS320C5515 , TMS320C5535

 

  1.   TMS320C5505/15/35/45 schematic checklist
    1.     Trademarks
    2. 1 Introduction
      1. 1.1 Device Applicability
      2. 1.2 Links to TI Hardware Designs Based on C5505/15/35/45
        1. 1.2.1 C5505 eZdsp
        2. 1.2.2 C5515 eZdsp
        3. 1.2.3 C5515 EVM
        4. 1.2.4 C5535 eZdsp
        5. 1.2.5 C5535 Audio Capacitive Touch BoosterPack
        6. 1.2.6 C5545 BoosterPack (BOOST5545ULP)
      3. 1.3 EVM vs Data Sheet
    3. 2 Complimentary Resources
    4. 3 Recommendations Specific to C5504/05/14/15/32/33/34/35/45
      1. 3.1  Before You Begin
        1. 3.1.1 Documentation
        2. 3.1.2 Pin Out
      2. 3.2  Unused Pins
      3. 3.3  Unused Power Rails
        1. 3.3.1 If USB is not Used
        2. 3.3.2 If RTC is not Used
        3. 3.3.3 If EMIF is not Used (not applicable to C5532/33/34/35 or C5545)
        4. 3.3.4 If an On-Chip LDO Output is not Used
      4. 3.4  Clocking
      5. 3.5  OSC Internal Oscillator Clock Source
      6. 3.6  Power
        1. 3.6.1 CVDDRTC Must be Always Supplied - [0.998 V - 1.43 V]
        2. 3.6.2 LDOI Must be Always Supplied
        3. 3.6.3 On-Chip LDOs
        4. 3.6.4 Recommended PMIC
        5. 3.6.5 DVDDIO Supply ON While CVDD OFF
        6. 3.6.6 Power Sequencing
        7. 3.6.7 Voltage Rails of IO Pins
      7. 3.7  Decoupling Capacitors
      8. 3.8  LDO Output Decoupling Capacitors
      9. 3.9  Digital GND, Analog GND, Local GND
        1. 3.9.1 Recommended USB Supplies
      10. 3.10 Reset
      11. 3.11 USB
      12. 3.12 I2C
      13. 3.13 I2S
      14. 3.14 RTC
      15. 3.15 SAR ADC
      16. 3.16 Pin Muxing
      17. 3.17 Signal Visibility
      18. 3.18 EMIF (not applicable to C5532/33/34/35 or C5545)
      19. 3.19 JTAG
      20. 3.20 Bootloader
    5. 4 References

3.11 USB

  • Plan to route USB differential pair signals first, on top layer if possible
  • Avoid stubs, differential pair length mismatch or impedance mismatch
  • Avoid any discrete components in DP/DM trace (except USB.org approved ESD components)
  • See High-Speed Interface Layout Guidelines
  • This USB peripheral is USB 2.0 high speed - do not implement USB 1.0 circuit on DP/DM pins

  • USB 1.0 circuit has series resistors and capacitors to GND on the DP and DM lines
  • USB 2.0 circuit has no components (except USB.org high-speed approved ESD components)
  • Implementing a USB 1.0 circuit on USB 2.0 will impact high-speed performance

  • For USB power sequence requirements, see Section 3.6.6
  • Caution: If USBVDD_OSC is ON while CVDD is OFF, the USB oscillator is enabled and consumes power

  • Having I/O power supplied while CORE power is off is an allowable power configuration, see Section 3.6.5
  • Register settings are lost when CVDD is OFF - USBOSCDIS in the USBSCR register loses its state
  • Prevent power consumption by turning USBVDD_OSC OFF before CVDD is OFF

  • USB_R1 - the USB_R1 resistor (reference current output) may need to be tweaked to pass USB compliance - perform the USB eye mask test on the board and adjust the resistor value until the eye is passing with margin. 8k - 10k is the range for most boards.

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