SNVU753A November   2019  – May 2021 TPS542A52

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Before You Begin
  3. 2Description
    1. 2.1 Typical End-User Applications
    2. 2.2 EVM Features
    3. 2.3 TPS542A52EVM-059 PCB
  4. 3TPS542A52EVM-059 Bottom Circuit
    1. 3.1 Modifications
      1. 3.1.1 Output Voltage Setpoint
      2. 3.1.2 Enable and Undervoltage Lockout
      3. 3.1.3 External Clock Synchronization
      4. 3.1.4 Load Step with Function Generator
    2. 3.2 Bottom Circuit Schematic
    3. 3.3 Test Setup and Results
      1. 3.3.1  Input/Output Connections
      2. 3.3.2  Start Up Procedure
      3. 3.3.3  Electrical Performance Specifications and Results
      4. 3.3.4  Efficiency
      5. 3.3.5  Power Loss
      6. 3.3.6  Load Regulation
      7. 3.3.7  Transient Response
      8. 3.3.8  Loop Response
      9. 3.3.9  Output Voltage Ripple
      10. 3.3.10 Thermal Data
  5. 4TPS542A52EVM-059 Top Circuit (Small Layout Area Design)
    1. 4.1 Modifications
      1. 4.1.1 Output Voltage Setpoint
      2. 4.1.2 Enable and Undervoltage Lockout
      3. 4.1.3 External Clock Synchronization
      4. 4.1.4 Load Step with Function Generator
    2. 4.2 TPS542A52EVM-059 Top Circuit (Small Layout Area) Schematic
    3. 4.3 Test Setup and Results
      1. 4.3.1  Input/Output Connections
      2. 4.3.2  Start Up Procedure
      3. 4.3.3  Electrical Performance Specifications and Results
      4. 4.3.4  Efficiency
      5. 4.3.5  Power Loss
      6. 4.3.6  Load Regulation
      7. 4.3.7  Line Regulation
      8. 4.3.8  Transient Response
      9. 4.3.9  Loop Response
      10. 4.3.10 Output Voltage Ripple
      11. 4.3.11 Start Up
  6. 5TPS542A52EVM-059 PCB Layout
  7. 6List of Materials
  8. 7Revision History

3.1.3 External Clock Synchronization

An external signal (recommended 0-V to 3.3-V) can be used as an external clock synchronization source. To use this feature, the TPS542A52 must be enabled, either by pulling the EN pin high or leaving it floating as described in Section 3.1.2. A jumper should be placed between J3-2 and J3-3, and the external clock signal should be applied to the SYNC_CLK (TP12) test point, referenced to AGND. The external clock synchronization signal applied to the SYNC pin must also be within -10% to +10% of the configured switching frequency.