SNVAA30 December   2021 LM5170-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Commercial Vehicle Power System
    2. 1.2 Operation of Battery Equalizer
  3. 2Designing Buck Converter with LM5170-Q1
    1. 2.1 VHV to VLV Buck Converter with 13-A Maximum Output Current
    2. 2.2 Inner Current Loop Design
    3. 2.3 Outer Voltage Loop Design
    4. 2.4 Implementation of Current Limit
  4. 3Experimental verification
  5. 4Conclusion
  6. 5References

2.3 Outer Voltage Loop Design

To implement outer voltage loop, an external Op-Amp (Texas Instruments LM6142) is used. The Op-Amp keeps constant ratio between VHV and VLV. The non-inverting input of the Op-Amp is connected to the 9R:1R resistor divider on the VHV rail, and the inverting input is fed by the 4R:1R resistor divider on the VLV rail. Therefore, the Op-Amp’s non-inverting input voltage is at 1R/10R × VHV, and the inverting input at 1R/5R × VLV. In the closed loop operation, VHV = 2 × VLV, namely the two battery voltages are balanced.

GUID-20211201-SS0I-MNGL-5FJ0-XNJR048QKZCG-low.gif Figure 2-4 Outer Voltage Loop Control in LM5170-Q1

A Type II compensation network is used to stabilize the outer voltage loop. Figure 2-4 shows configuration of type II compensation network consisting of RCOMP2, CCOMP2 , and CHF2. The introduced poles and zero of compensation network are determined by

Equation 9. F P _ P L A N T = 1 2 π × R L × C o    
Equation 10. F P _ C O M P = 1 2 π × R C O M P 2 × C H F 2  
Equation 11. F Z _ C O M P = 1 2 π × R C O M P 2 × C C O M P 2  

where RL is load equivalent resistance and Co is output capacitance.

To tailor the total voltage loop gain to cross over at FCO_VOL, select components of the compensation network according to the following guidelines, then fine tune the network for optimal loop performance.

  1. The FCO_VOL is set to 1/5 or 1/10 of FCO_CUR
  2. The total outer voltage loop gain is set to unity at FCO_VOL
  3. The zero FZ_COMP is placed at the power stage power FP_PLANT
  4. The pole FP_COMP is placed at approximately one or two decades higher than FZ_COMP, but lower than FSW

Select RCOMP2 = 270 kΩ, CCOMP2 = 2.7 nF, and CHF2 = 13 pF which can meet the following equations.

Equation 12. F C O _ V O L = 1 5 × F C O _ C U R = 3.98   k H z    
Equation 13. F P _ P L A N T = 1 2 π × 0.92 Ω × 740 u F = 234   H z  
Equation 14. F Z _ C O M P = 1 2 π × 270   k Ω × 2.7   n F   = 218   H z
Equation 15. F P _ C O M P = 1 2 π × 270   k Ω × 13   p F = 45.34   k H z
Figure 2-5 Bode Plot of Outer Voltage Loop

Figure 2-5 shows bode plot of outer voltage loop. Phase in mid-frequency range is boosted by type II compensation network. In this example, the crossover frequency is at about 4 kHz, and the phase margin is approximately 75 degree, which is greatly higher than the needed minimal 45 degree of a stable system. FP_COMP is placed at 45.34 kHz which is lower than switching frequency (99.5 kHz) to minimize output ripple caused by MOSFET switching.