SNOU172 December   2020 LM74500-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Setup
    1. 2.1 I/O Connector Description
    2. 2.2 Board Setup
    3. 2.3 Schematic
  4. 3Operation
    1. 3.1 LM74500Q1EVM Performance Capture
  5. 4EVM Board Assembly Drawings and Layout Guidelines
    1. 4.1 PCB Drawings
    2. 4.2 Bill of Materials

LM74500Q1EVM Performance Capture

A startup pulse from 0 V to 12 V is applied at the input of the LM74500Q1EVM. Figure 3-1 shows the input voltage (CH1) rises from 0 V to 12 V and the gate voltage (CH3) comes up after input voltage crosses device PoR threshold . The gate of external N-FET is fully enhanced and FET is turned on. Output voltage (CH2) rises smoothly from 0 V to 12 V.

GUID-20201208-CA0I-1FKV-RWVS-VM3VDRNPPJCP-low.png Figure 3-1 LM74500Q1EVM Startup

A –12 V source is connected to the VIN input of the LM74500Q1EVM. Figure 3-2 shows that the output voltage remains at a constant 0 V in this situation. This test simulates the event of connecting a 12-V battery in the reverse direction; therefore, protecting the load from negative input voltages.

GUID-20201208-CA0I-G45N-TN1V-BBN877XDTL9P-low.png Figure 3-2 Startup Reverse Polarity (–12 V)