SNLU317A september   2022  – may 2023 DP83867E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
    2. 1.2 Hardware Features
    3. 1.3 Software Features
    4. 1.4 Block Diagram
  5. 2Board Overview
    1. 2.1 Components
    2. 2.2 PCIe Header Signals
      1. 2.2.1 MISC0 Signal Header
      2. 2.2.2 MISC1 Signal Header
      3. 2.2.3 RGMII Signal Header
  6. 3Quick Start
  7. 4Schematic, Board Layout, and Bill of Materials
    1. 4.1 Board Layout
    2. 4.2 Schematic
    3. 4.3 Bill of Materials
  8. 5Revision History

Schematic

GUID-20220725-SS0I-M3HC-SRFT-GKRTJTPNPLR1-low.svg Figure 4-3 Schematic : PCIe Host Interface
GUID-20220725-SS0I-7WND-QJR0-4HPW8CSQBKRQ-low.svg Figure 4-4 Schematic : DP83867 Ethernet PHY #1
GUID-20220725-SS0I-5L7N-RL1H-FPGSTV8B1QBS-low.svg Figure 4-5 Schematic : DP83867 Ethernet PHY #2
GUID-20220725-SS0I-LSGW-RVSR-FZ6CTT2XLHJB-low.svg Figure 4-6 Schematic : Ethernet Fiber interface
GUID-20230426-SS0I-DQF3-DCJC-FRS2W1Z66LQX-low.svg Figure 4-7 Schematic : Power, Clock and Configuration