SNAK010 April   2022 ADC128S102-SEP

 

  1.   Trademarks
  2. 1Device Information
    1. 1.1 Device Details
  3. 2Total Dose Test Setup
    1. 2.1 Test Overview
    2. 2.2 Test Description and Facilities
    3. 2.3 Test Setup Details
      1. 2.3.1 Biased
    4. 2.4 Test Configuration and Condition
  4.   A Total Ionizing Dose HDR Report Appendix

2.3.1 Biased

Figure 2-1 shows the bias conditions for each pin during irradiation. Table 2-1 describes the pin signal connections.

GUID-D104DD98-5343-4324-BDEB-D736554610DC-low.pngFigure 2-1 ADC128S102PW-SEP Biased Diagram
Table 2-1 Pin Signal Connections

Symbol

Limits

MIN

MAX

VA and VD

5.0 V

5.5 V

Vin

1.6 V

1.8 V

IDA and IDD

0.25 mA

0.33 mA

SCLK

50 kHz; 0 V–3.3 V

CS

2.5 kHz; 0 V–3.3 V

Table 2-2 lists the bill of materials for the TID bias board used.

Table 2-2 Bill of Materials

Refs Designator

Qty

Description

R1

4

50 OHMS, 1/4 WATT, 1%

C3

2

10uF, 35V, 5%

C4

2

0.1uF, 35V, 5%

C5

1

1000pF, 35V, 5%

SMB

2

SMB JACK Right Angle