SLVUDE1 July   2025 TPS65219-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Introduction
  6. 3TPS6521922W-Q1 Sequence and Power Block Diagram
  7. 4EEPROM Device Settings
    1. 4.1  Device ID
    2. 4.2  Enable Settings
    3. 4.3  Regulator Voltage Settings
    4. 4.4  Sequence Settings
      1. 4.4.1 Power-Up Sequence
      2. 4.4.2 Power-Down Sequence
    5. 4.5  EN / PB / VSENSE Settings
    6. 4.6  Multi-Function Pin Settings
    7. 4.7  Over-Current Deglitch
    8. 4.8  Mask Settings
    9. 4.9  Discharge Check
    10. 4.10 Multi PMIC Config
  8. 5Revision History

4 EEPROM Device Settings

The following sections describe the default configuration on the EEPROM-backed registers. During the power-down-sequence, non-EEPROM-backed bits are reset, with the exception of unmasked interrupt bits and DISCHARGE_EN bits.