SLVUCL9A June   2023  – February 2025 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  TPS6521907 Sequence and Power Block Diagram
    3. 2.3  Enable Settings
    4. 2.4  Regulator Voltage Settings
    5. 2.5  Sequence Settings
      1. 2.5.1 Power-Up Sequence
      2. 2.5.2 Power-Down Sequence
    6. 2.6  EN / PB / VSENSE Settings
    7. 2.7  Multi-Function Pin Settings
    8. 2.8  Over-Current Deglitch
    9. 2.9  Mask Settings
    10. 2.10 Discharge Check
    11. 2.11 Multi PMIC Config
  6. 3Revision History

2 EEPROM Device Settings

The following sections describe the default configuration on the EEPROM-backed registers. During the power-down-sequence, non-EEPROM-backed bits are reset, with the exception of unmasked interrupt bits and DISCHARGE_EN bits.