SLVUCL9A June   2023  – February 2025 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  TPS6521907 Sequence and Power Block Diagram
    3. 2.3  Enable Settings
    4. 2.4  Regulator Voltage Settings
    5. 2.5  Sequence Settings
      1. 2.5.1 Power-Up Sequence
      2. 2.5.2 Power-Down Sequence
    6. 2.6  EN / PB / VSENSE Settings
    7. 2.7  Multi-Function Pin Settings
    8. 2.8  Over-Current Deglitch
    9. 2.9  Mask Settings
    10. 2.10 Discharge Check
    11. 2.11 Multi PMIC Config
  6. 3Revision History

2.10 Discharge Check

Active discharge is enabled by default and is not NVM based. If desired, this setting can be disabled after each VSYS-power-cycle. During RESET or OFF-request, the discharge configuration is not reset, as long as VSYS is present. However, in INITIALIZE state and prior to the power-up-sequence, all rails are discharged, regardless of the setting. In case active discharge on a rail is disabled, it does not gate the disable of the subsequent rail, but the sequence is purely timing based. In case of residual voltage, the RV-bit is set regardless.

Table 2-16 Discharge Check
Register Address Field Name Value Description
0x1E BYPASS_RAILS_DISCHARGED_CHECK 0x0 Discharged checks enforced