SLVUC09 September   2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification
    3. 1.3 Modifications
      1. 1.3.1 IC U1 Operation
      2. 1.3.2 Device Enable Evaluation
  3. 2Setup
    1. 2.1 Input/Output Connector and Header Descriptions
    2. 2.2 Setup
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials

3.1 Layout

Figure 3-1 and Figure 3-2 show the board layout for the TPS631000EVM-075 PCB.

GUID-20210927-SS0I-Z0FG-NFHV-KFT1ZNTQJDK8-low.gif Figure 3-1 Top Layer Routing
GUID-20210927-SS0I-V27L-X1VC-VP0GBBTGVXZS-low.gif Figure 3-2 Bottom Layer Routing