5 LET_EFF and Range Calculation

Figure 5-1 Generalized Cross-Section of the RFSiGe Technology BEOL Stack on the CDCLVP111-SEP [Left] and GUI of RADsim-IONS Application (Right)

The CDCLVP111-SEP is fabricated in the TI RFSiGe process with a back-end-of-line (BEOL) stack consisting of 4 levels of standard thickness aluminum. The total stack height from the surface of the passivation to the silicon surface is 8512 μm based on nominal layer thickness as shown in Figure 5-1.

Accounting for energy loss through the degrader, copper foil, beam port window, air gap, and the BEOL stack of the CDCLVP111-SEP, the effective LET (LET_EFF) at the surface of the silicon substrate and the range was determined with:

• SEUSS 2024 software (provided by TAMU and based on the latest SRIM-2013 [7] models)

The results are shown in Ion LET_EFF and Range in Silicon.