SLVK222 August   2025 TPS7H5020-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. Introduction
  5. Single-Event Effects (SEE)
  6. Device and Test Board Information
  7. Irradiation Facility and Setup
  8. LETEFF and Range Calculation
  9. Test Setup and Procedures
  10. Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. Single-Event Transients (SET)
  12. Event Rate Calculations
  13. 10Summary
  14.   A References

Single-Event Transients (SET)

SET are defined as heavy-ion-induced transients upsets on the GATE (OUTH and OUTL tied together), REFCAP, VLDO, and SS of the TPS7H502X-SP. When conducting testing on the device in flyback configuration the VOUT of the device (the DC signal after the transformer on the EVM) was also monitored.

Testing was performed at room temperature (no external temperature control applied). The heavy-ions species used for the SET testing was 165Ho at 15 MeV/nucleon and 169Tm at 19.5 MeV/nucleon (for more details refer to Ion LETEFF and Range in Silicon). Flux of ≈105 ions×cm2/s and a fluence of ≈107 ions/cm2, per run were used for the SET characterization discussed in this chapter.

Waveform size, sample rate, trigger type, value, and signal for all scopes used is presented on Table 8-1.

Note1: Only one Signal was used as a trigger source at a time, this table presents all possible sources for a given scope, the same is valid for the trigger type. All percentage specified on the trigger value are deviation from the nominal value.

Note2: The trigger signal VOUT is only valid for and was only monitored during the flyback configuration testing on the flyback EVM.

Table 8-1 Scope Settings

Scope Model

Trigger Signal1

Trigger Type

Trigger Value

Record Length

Sample Rate

PXIe-5110

GATE

Pulse-Width ± 20%

50k

100MS/s

PXIe-5172 (1)

REFCAP

Window

± 3 %

50k

100MS/s

PXIe-5172 (2)

VLDO

Window

± 3 %

50k

100MS/s

PXIe-5162

SS

Edge/Negative 0.5V

50k

100MS/s

PXIe-5172 (3)

VOUT2

Window

± 3 %

50k

100MS/s

Open-Loop Configuration

The primary focus of SETs were heavy-ion-induced transient upsets on output signal GATE (OUTH and OUTL tied together). SET testing was done at room temperature at 165Ho which produced a LETEFF of 75 MeV·cm2/mg. GATE was monitored using a NI PXIe-5110. During testing the scope was set to trigger if the signal exceeded |20%| from nominal using a pulse width trigger. During all SET testing, there was one type of transient recorded that was self-recoverable. The REFCAP, VLDO, and SS signals monitored on the PXIe-5172 and PXIe-5162 scopes did not have any recorded transients. Because the VLDO signal had a window trigger on it, being transient free shows that there is no overshoot on the device at 75 MeV·cm2/mg.

The SET results for 2 production and 7 pre-production devices are shown below in the following tables. The transient signature on GATE is shown and the number of transients across the runs, voltages, and frequencies is shown. Since only this transient signature occurred there is high confidence that the TPS7H502X-SP is SEFI free and the recorded transient signature does not show any overshoot indicating that the TPS7H502X-SP is safe for GaN operations. Note that for all testing VLDO was programmed to be 5V except for the cases where VIN=PVIN=4.5V in which case it was programmed to be 4.5V as well.

The upper-bound cross-sections for all bias conditions are shown inFigure 8-1.

Table 8-2 Summary of TPS7H502X-SP Open-Loop SET Test Condition and Results
RUN #UNIT #

Facility

Device Type

Production Type

Mode

VIN (V)

FSW (Hz)

IONLETEFF (MeV·cm2/mg)FLUX (ions×cm2/s)FLUENCE (ions/cm2)# GATE ≥ |20%|# REFCAP ≥ |3%|

# VLDO ≥ |3%|

# SS Triggers

40

2

TAMU

TPS7H5020-SP

Pre

Silicon

12

500k

165Ho

75

1.00 × 105

1.00 × 107

51

0

0

0

41

2

TAMU

TPS7H5020-SP

Pre

Silicon

12

100k

165Ho

75

1.00 × 1051.00 × 107

22

0

0

0

42

2

TAMU

TPS7H5020-SP

Pre

Silicon

12

1M

165Ho

75

1.00 × 1051.00 × 107

0

0

0

0

43

2

TAMU

TPS7H5020-SP

Pre

GaN

4.5

1M

165Ho

75

1.00 × 1051.00 × 107

0

0

0

0

44

2

TAMUTPS7H5020-SPPreGaN

4.5

1M165Ho751.00 × 1051.00 × 107

0

0

0

0

45

2

TAMUTPS7H5020-SPPreGaN

4.5

1M165Ho751.00 × 1051.00 × 107

0

0

0

0

46

2

TAMUTPS7H5020-SPPreGaN

4.5

100k165Ho751.00 × 1051.00 × 107

66

0

0

0

47

2

TAMUTPS7H5020-SPPreGaN

4.5

500k165Ho751.00 × 1051.00 × 107

43

0

0

0

48

2

TAMUTPS7H5020-SPPreSilicon

12

100k165Ho751.00 × 1051.00 × 107

32

0

0

0

49

2

TAMUTPS7H5020-SPPreSilicon

12

500k165Ho751.00 × 1051.00 × 107

42

0

0

0

50

3

TAMUTPS7H5020-SPPreGaN

12

500k165Ho751.00 × 1051.00 × 107

0

0

0

51

3

TAMUTPS7H5020-SPPreGaN

12

500k165Ho751.00 × 1051.00 × 107

45

0

0

0

52

3

TAMUTPS7H5020-SPPreGaN

12

100k165Ho751.00 × 1051.00 × 107

48

0

0

0

53

3

TAMUTPS7H5020-SPPreGaN

12

1M165Ho751.00 × 1051.00 × 107

4

0

0

0

54

3

TAMUTPS7H5020-SPPreGaN

12

500k165Ho751.00 × 1051.00 × 107

59

0

0

0

55

3

TAMUTPS7H5020-SPPreSilicon

12

500k165Ho751.00 × 1051.00 × 107

16

0

0

0

56

3

TAMUTPS7H5020-SPPreGaN

12

500k165Ho751.00 × 1051.00 × 107

41

0

0

0

57

3

TAMUTPS7H5020-SPPreGaN

12

500k165Ho751.00 × 1051.00 × 107

37

0

0

0

58

4

TAMUTPS7H5021-SPPreSilicon

12

500k165Ho751.00 × 1051.00 × 107

73

0

0

0

59

4

TAMUTPS7H5021-SPPreSilicon

12

100k165Ho751.00 × 1051.00 × 107

40

0

0

0

60

4

TAMUTPS7H5021-SPPreSilicon

12

1M165Ho751.00 × 1051.00 × 107

0

0

0

0

61

4

TAMUTPS7H5021-SPPreGaN

4.5

1M165Ho751.00 × 1051.00 × 107

3

0

0

0

62

4

TAMUTPS7H5021-SPPreGaN

4.5

500k165Ho751.00 × 1051.00 × 107

62

0

0

0

63

4

TAMUTPS7H5021-SPPreGaN

4.5

100k165Ho751.00 × 1051.00 × 107

78

0

0

0

64

5

TAMUTPS7H5021-SPPreGaN

12

500k165Ho751.00 × 1051.00 × 107

21

0

0

0

65

5

TAMUTPS7H5021-SPPreGaN

12

100k165Ho751.00 × 1051.00 × 107

41

0

0

0

66

5

TAMUTPS7H5021-SPPreGaN

12

1M165Ho751.00 × 1051.00 × 107

6

0

0

0

67

5

TAMUTPS7H5021-SPPreGaN

4.5

1M165Ho751.00 × 1051.00 × 107

0

0

0

0

68

5

TAMUTPS7H5021-SPPreGaN

4.5

500k165Ho751.00 × 1051.00 × 107

39

0

0

0

69

5

TAMUTPS7H5021-SPPreGaN

4.5

100k165Ho751.00 × 1051.00 × 107

47

0

0

0

70

6

TAMUTPS7H5021-SPPreGaN

12

500k165Ho751.00 × 1051.00 × 107

31

0

0

0

71

6

TAMUTPS7H5021-SPPreGaN

12

500k165Ho751.00 × 1051.00 × 107

42

0

0

0

72

6

TAMUTPS7H5021-SPPreGaN

12

500k165Ho751.00 × 1051.00 × 107

25

0

0

0

73

14

TAMUTPS7H5020-SP

Final

GaN

12

500k165Ho75

1.11 × 105

1.00 × 107

123

74

14

TAMUTPS7H5020-SPFinalSilicon

12

500k165Ho75

1.13 × 105

1.00 × 107

41

75

15

TAMUTPS7H5021-SPFinalGaN

12

500k165Ho75

1.18 × 105

1.00 × 107

173

76

15

TAMUTPS7H5021-SPFinal

Silicon

12

500k

165Ho75

1.16 × 105

1.00 × 107

55

77

12

KSEE

TPS7H5020-SP

Final

Silicon

12

500k

169Tm

75

9.87 × 104

1.00 × 107

64

78

13

KSEE

TPS7H5021-SP

Final

Silicon

12

500k

169Tm

75

1.06 × 105

1.00 × 107

79

83

16

KSEE

TPS7H5020-SP

Pre

Silicon

12

500k

109Ag

49.1

9.70 × 104

1.00 × 107

5

84

17

KSEE

TPS7H5020-SP

Pre

GaN

12

500k

109Ag

49.1

1.20 × 105

1.00 × 107

44

 TPS7H5020-SP Silicon Mode GATE Pulse-Width TransientFigure 8-1 TPS7H5020-SP Silicon Mode GATE Pulse-Width Transient
 TPS7H5020-SP Silicon Mode GATE Pulse-Width Deviation HistogramFigure 8-2 TPS7H5020-SP Silicon Mode GATE Pulse-Width Deviation Histogram
 TPS7H5020-SP GaN Mode GATE Pulse-Width TransientFigure 8-3 TPS7H5020-SP GaN Mode GATE Pulse-Width Transient
 TPS7H5020-SP GaN Mode GATE Pulse-Width Deviation HistogramFigure 8-4 TPS7H5020-SP GaN Mode GATE Pulse-Width Deviation Histogram
 TPS7H5021-SP Silicon Mode GATE Pulse-Width TransientFigure 8-5 TPS7H5021-SP Silicon Mode GATE Pulse-Width Transient
 TPS7H5021-SP Silicon Mode GATE Pulse-Width Deviation HistogramFigure 8-6 TPS7H5021-SP Silicon Mode GATE Pulse-Width Deviation Histogram
 TPS7H5021-SP GaN Mode GATE Pulse-Width TransientFigure 8-7 TPS7H5021-SP GaN Mode GATE Pulse-Width Transient
 TPS7H5021-SP GaN Mode GATE Pulse-Width Deviation HistogramFigure 8-8 TPS7H5021-SP GaN Mode GATE Pulse-Width Deviation Histogram
Table 8-3 TPS7H502X-SP SET Cross-Sections

LETEFF (MeV·cm2/mg)

Mode

Parameters

VIN

(V)

Fluence (ions/cm2)

# Transients

Upper-Bound Cross-Section (cm2)

75

Silicon

100k 12

3 × 107

94

3.83 × 10-6

500k

8 × 107

421

5.79 × 10-6

1M

2 × 107

0

1.84 × 10-7

GaN

100k 4.5

3 × 107

191

7.34 × 10-6

12

2 × 107

89

5.48 × 10-6

500k

4.5

3 × 107

144

5.65 × 10-6

12

1 × 108

597

6.47 × 10-6

1M

4.5

5 × 107

3

1.75 × 10-7

12

2 × 107

10

9.20 × 10-6

48

Silicon

500k

12

1 × 107

5

1.17 × 10-6

GaN

500k

12

1 × 107

44

5.91 × 10-6

Flyback Configuration

To better understand functionality of the device closed-loop testing was conducted with the device in a flyback configuration. A flyback EVM was designed to allow the device to operate as a flyback converter with a power stage input voltage of 28V and an output voltage of 5V. During this testing TPS7H502X-SP was powered to operate in GaN mode with a nominal voltage of 12V at VIN, PVIN tied to VLDO at 5V, and loaded to a 4A load on the output. The load was provided by a Chroma E-Load in constant resistance mode with a resistance of 1.25Ω. During the testing the GATE (OUTH and OUTL tied together before the transformer) signal and VOUT (the DC output signal after the transformer) were monitored by a PXIe-5110 and PXIe-5172 respectively. Testing was done at room temperature at 165Ho which produced a LETEFF of 75MeV·cm2/mg. During testing the PXIe-5110 scope was set to trigger if the signal exceeded |20%| from nominal using a pulse width trigger. For VOUT the PXIe-5172 was set to trigger on a |3%| window. During all SET testing, there were three types of transients recorded on GATE that were all self-recoverable. The first was a long transient only seen during the beginning of the run when the beam shutter opened. The second was a greater than +20% pulse-width transient. The third was a less than -20% pulse-width transient. There were no transients observed on VOUT during this testing indicating that the DC output of the flyback is transient free at the specified operating conditions at 75MeV·cm2/mg.

Table 8-4 Summary of TPS7H502X-SP Flyback Configuration SET Test Conditions and Results
RUN # UNIT # VIN (V) Power Stage (V) FSW (Hz) Load (A) ION LETEFF (MeV·cm2/mg) FLUX (ions×cm2/s) FLUENCE (# ions) #GATE ≥ |20%| VOUT # ≥ |3%|
79 18 12 28 500k 4 165Ho 75 5.00 × 104 1.00 × 107 58 0
80 19 12 28 500k 4 165Ho 75 5.00 × 104 1.00 × 107 49 0
81 20 12 28 500k 4 165Ho 75 5.00 × 104 1.00 × 107 39 0
82 21 12 28 500k 4 165Ho 75 5.00 × 104 1.00 × 107 48 0
 GATE transient during beam
                    shutter open Figure 8-9 GATE transient during beam shutter open
 Typical Gate Transient
                    >+20% Pulse-Width Deviation Figure 8-10 Typical Gate Transient >+20% Pulse-Width Deviation
 Typical Gate Transient <
                    -20% Pulse-Width Deviation Figure 8-11 Typical Gate Transient < -20% Pulse-Width Deviation