SLUUDN8 July   2026 TMS320F28P550SJ , TMS320F28P650DK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Library Notice
  6. 3Library Architecture
    1. 3.1 Background Processing
    2. 3.2 Foreground Processing
    3. 3.3 Data Transfer Mechanism
  7. 4Metrology Calculations
  8. 5Configuration and Data Structures
  9. 6Calibration Module
  10. 7User Specific Configurations
    1. 7.1 Debug Mode
      1. 7.1.1 The Function of Debug Mode
      2. 7.1.2 How to Configure DEBUG Mode Parameters
    2. 7.2 ADC Mode
      1. 7.2.1 Using the On-Chip ADC
      2. 7.2.2 Two Point Calibration
        1. 7.2.2.1 Step 1 – Offset Calibration (Zero-Input Point)
        2. 7.2.2.2 Step 2 – Gain Calibration (Full-Scale Point)
      3. 7.2.3 Using an External ADC
    3. 7.3 Switching Between Modes
    4. 7.4 THD Algorithm Selection
      1. 7.4.1 Method 1 – Based on PLL (Default When the HARMONICS_SUPPORT Macro is Not Defined)
      2. 7.4.2 Method 2 – Goertzel DFT (When the HARMONICS_SUPPORT and USE_GOERTZEL_THD Macros are Both Defined)
      3. 7.4.3 Method 3 – 2048-Point Real FFT (When the HARMONICS_SUPPORT Macro is Defined But the USE_GOERTZEL_THD Macro is Not)
    5. 7.5 Topology Selection
    6. 7.6 Enable Features
    7. 7.7 System Parameters
    8. 7.8 Scaling Factors Per Phase
  11. 8Running the Example
    1. 8.1 Accessing the Parameters Per Phase
    2. 8.2 Accessing the Total System Measurements
    3. 8.3 Accessing the Phase Status Flags

7.2.1 Using the On-Chip ADC

The on-chip ADC is configured entirely through the system configuration (.syscfg) file included in the project. Open the .syscfg file in the SysConfig menu to configure:

  • ADC module selection (ADCA for voltage, ADCB for current by default)
  • SOC (start of conversion) trigger source – Set to the same CPUTimer0 period used by the metrology ISR
  • Sampling window duration – Set to meet the ADC input circuit settling time
  • Acquisition window and EOC (end of conversion) interrupt if required

After saving the .syscfg file, the SysConfig menu regenerates the board.h header file and board.c source file with the peripheral names (myADC0_RESULT_BASE, myADC0_SOC0, and so forth) that the library uses.

Open the adc_config.h header file and assign the generated names to the library macros for each phase:

Phase A (always required):

  • ADC_VA_RESULT | ADC_VA_SOC – Result base and SOC number for the Phase A voltage channel.
  • ADC_IA_BASE | ADC_IA_RESULT | ADC_IA_SOC – Base address, result base, and SOC number for the phase A current channel.

Phase B (required for TWO_PHASE_SUPPORT, THREE_PHASE_SUPPORT, or SPLIT_PHASE_SUPPORT):

  • ADC_VB_RESULT | ADC_VB_SOC – Phase B voltage channel.
  • ADC_IB_RESULT | ADC_IB_SOC – Phase B current channel.

Phase C (required for THREE_PHASE_SUPPORT only, currently commented out, remove comment THREE_PHASE_SUPPORT when a third ADC is added in the SysConfig GUI):

  • ADC_VC_RESULT | ADC_VC_SOC – Phase C voltage channel. A third ADC SOC must be added in the SysConfig menu first.
  • ADC_IC_RESULT | ADC_IC_SOC – Phase C current channel.