8 TLVR-Optimized Components

Recently, semiconductor vendors such as Texas Instruments (TI) have begun to offer multiphase controllers and power stages optimized for TLVR designs.

Smart power stages optimized for TLVR designs require higher-bandwidth current-sensing architectures because of the high-speed nature of the TLVR topology. The IOUT pin waveform of a TI smart power stage, for example, tracks even the induced current ripple from the L_C loop in a TLVR design. This requires current-sensing bandwidth at least an order of magnitude higher than the f_SW of the design on a per-phase basis. The TLVR topology also increases the bandwidth requirements for high-speed overcurrent protection.

Smart power stages optimized for TLVR designs must also be rated for increasingly high RMS currents and be able to support peak current pulses nearly two times their RMS rating for short durations, thermally as well as electrically.

Controllers generally do not need re-architecting. TLVR designs use the same control schemes designed for multiphase buck designs. TI controllers continue to use the DCAP+ control architecture, a form of constant on-time valley current-mode control. They may still require second-order optimizations such as new gain and compensation parameters suited to the TLVR powertrain. Higher-strength PWM output drivers are often needed to support longer distances between multiple L_C loops while maintaining good signal integrity. The implementation of a new protection mechanism for an open or shorted L_C loop should ease manufacturability concerns.

Table 3 and Table 4 summarize TLVR-optimized components available from TI at the time of this writing, with more under development.