In second chapter, it introduces system and bode plot of DCAP2 topology. It’s suggested to put double pole frequency marginally smaller than internal zero frequency. The internal zero can boost phase higher. So the system can get a larger bandwidth and a higher phase margin at crossover frequency. The internal zero frequency of TPS563202 is 24kHz, So it’s good to put double pole frequency to about 20kHz as Equation 5. Output capacitance Cout is received from Equation 6.

Equation 5.

Equation 6.

MLCC capacitance is widely used in application because of its small size, low ESR and good price. But degrading of MLCC capacitance is very large when adding a DC bias voltage, especially at higher DC bias voltage. The degrading couldn’t be ignored in calculating output capacitance. It introduces an example of MuRata capacitance GRM21BR61A226ME44 which is 10V, 22uF, and 0805 footprint. Figure 2-5 is degrading curve. From the figure, the capacitance degrades by 50% at 5V bias voltage. If the MLCC capacitance rated voltage is smaller, or footprint is smaller, it degrades much larger. In the calculation of output capacitance, the degrading of MLCC capacitance could not be ignored.

Figure 2-5 GRM21BR61A226ME44 C-DC Bias Voltage