SLUAA80 November   2020 TPS40322

 

  1.   Trademarks
  2. 1Introduction
  3. 2Circuit Description
    1. 2.1 Calculation for VOUT Settings
  4. 3Setup TPL0102-100 EVM
    1. 3.1 Connection Block Diagram
    2. 3.2 Software GUI Setup
  5. 4Conclusion

Calculation for VOUT Settings

Figure 2-2 shows the FB network circuit.

GUID-20201109-CA0I-BPP0-Q1FW-JSL0SX4SXGFN-low.gifFigure 2-2 FB Network.

Converter DC regulation forces VFB = VREF = 0.6 V. Therefore, the divider is injecting current iINJ into the FB node to offset the output voltage.

  1. Calculate VOUT as a function of iINJ

    KCL at FB node:

    Equation 1.
    GUID-20201106-CA0I-MGKC-XRSB-4VXZSGNLJSZS-low.gif

    Rearrange and simplify as Equation 2 shows:

    Equation 2.
    GUID-20201106-CA0I-1NFX-LHFD-Q75H0NQCJ85N-low.gif

  2. Solve for iINJ
    Equation 3.
    GUID-20201106-CA0I-9MBF-TX03-RZHXLRCVVTDL-low.gif

    KCL @ X to solve for Vx:

    Equation 4.
    GUID-20201106-CA0I-K3HZ-HWXD-W6BTBT57KGMD-low.gif

    Rearrange and simplify as Equation 5 shows:

    Equation 5.
    GUID-20201106-CA0I-MTFX-C9MS-MRF98GW67CPW-low.gif

  3. Substitute:
    Equation 6.
    GUID-20201106-CA0I-NZBQ-CHT3-WDHSLK6JKKTR-low.gif

    where Vx equals Equation 5.

These calculations are integrated in the TPS40322 Resistor Divider Vout Offset Calculator tool.