SLLSF86C May   2018  – March 2022

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description Continued
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  Recommended Operating Conditions
    3. 8.3  Thermal Information
    4. 8.4  Power Ratings
    5. 8.5  Insulation Specifications
    6. 8.6  Safety-Related Certifications
    7. 8.7  Safety Limiting Values
    8. 8.8  Electrical Characteristics
    9. 8.9  Supply Current Characteristics at VISOOUT = 3.3 V
    10. 8.10 Supply Current Characteristics at  VISOOUT = 5 V
    11. 8.11 Switching Characteristics at VISOOUT = 3.3 V
    12. 8.12 Switching Characteristics at VISOOUT = 5 V
    13. 8.13 Insulation Characteristics Curves
    14. 8.14 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Power Isolation
    3. 10.3 Signal Isolation
    4. 10.4 RS-485
    5. 10.5 Functional Block Diagram
    6. 10.6 Feature Description
      1. 10.6.1 Power-Up and Power-Down Behavior
      2. 10.6.2 Protection Features
      3. 10.6.3 Failsafe Receiver
      4. 10.6.4 Glitch-Free Power Up and Power Down
    7. 10.7 Device Functional Modes
    8. 10.8 Device I/O Schematics
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Data Rate, Bus Length and Bus Loading
        2. 11.2.2.2 Stub Length
        3. 11.2.2.3 Insulation Lifetime
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 Support Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

13.1 Layout Guidelines

Figure 11-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines must be followed to achieve low emissions design:

  1. High frequency bypass capacitors 10 nF must be placed close to VDD and VISOOUT pins, less than 1 mm distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure that these capacitors are 0402 size so that they offer least inductance (ESL).
  2. Bulk capacitors of atleast 10 µF must be placed on power converter input (VDD) and output (VISOOUT) supply pins.
  3. Traces on VDD and GND1 must be symmetric till bypass capacitors. Similarly traces on VISOOUT and GND2 must be symmetric.
  4. Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on power supply pins, one between VISOOUT and VISOIN and the other between GND2 (11) and GISOIN(15), as shown in example PCB layout, so that any high frequency noise from power converter output sees a high impedance before it goes to other components on PCB.
  5. Do not have any metal traces or ground pour within 4 mm of power converter output terminals VISOOUT (pin12) and GND2 (pin11). MODE pin is also in VISOOUT domain and should be shorted to either pin 11 or pin 12 for output voltage selection.
  6. Common mode choke or ferrite beads on bus terminals (Y/Z/A/B) can minimise any high frequency noise that can couple of RS-485 bus cable which can act as antenna and amplify that noise. This will improve Radiated emissions performance on a system level.
  7. Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated emissions design. EVM Link is available in Related Documentation.