SLLA591 June 2022 TDP1204
EN: When low, TDP1204 is held in reset. The EN pin has a internal 250k pull-up to VIO. For passive circuitry implementation, it is recommended to add an external 0.22 µF pulldown capacitor on the EN pin.
VIO: The TDP1204 supports 1.2-V, 1.8-V, and 3.3-V LVCMOS levels depending on the source I/O voltage requirement. The VIO pin is used to select which voltage level is used for the following 2-level control pins: LV_DDC_SDA, LV_DDC_SCL, SCL/CFG0, and SDA/CFG1.
VIO Pin | LVCMOS Signaling Level |
---|---|
VIO < 1.5 V | 1.2 V |
1.5 V < VIO < 2.5 V | 1.8 V |
VIO > 2.5 V | 3.3 V |
Mode (pin-strap or I2C mode): The MODE pin provides four modes of operation: three pin-strap modes and one I2C mode.
In pin-strap mode, if using the LV_DDC_SDA and LV_DDC_SCL for DDC snooping, the internal DDC buffer must be disabled. But, if using the HV_DDC_SDA and HV_DDC_SCL for DDC snooping, the internal DDC buffer must be enabled.
In I2C mode, DDC snoop feature is enabled by default but can be disabled by a register.
Mode | Description |
---|---|
0 | Pin-strap mode with internal DDC buffer enabled and fixed receiver equalizer |
R | Pin-strap mode with internal DDC buffer disabled and adaptive receiver equalizer |
F | I2C mode |
1 | Pin-strap mode with internal DDC buffer enabled and adaptive receiver equalizer |
SCL/CFG0: In pin-strap mode, this is the CFG0 pin. It is recommended to tie this pin to '0' for normal HDMI mode. In I2C mode, this is the SCL pin.
SDA/CFG1: In pin-strap mode, this is the CFG1 pin. The CFG1 pin needs to be set to '0' for normal lane ordering, but set to '1' if the input/output lane order is swapped. In I2C mode, this is the SDA pin.
LINEAR_EN pin: The TDP1204 supports both linear and limited redriver. In pin-strap mode, the LINEAR_EN sets the TDP1204 into either linear or limited redriver mode. It provides the option to dynamically switch between limited and linear based on the HDMI mode of operation. It is recommended to set the LINEAR_EN pin = "1".
GPU TX Transmitter | Min | Max | Units |
Single-ended SWING | 400 | 500 | mV |
Rise/Fall time for 3, 6, 8, 10, 12Gbps FRL | 16 | mV/ps |
HPDOUT_SEL: The HPDOUT_SEL selects whether the HPD_OUT pin is push/pull or open-drain. HPDOUT_SEL needs to be set to "0" for push/pull and set to "1" for open-drain.