SLAZ246Z October   2012  – May 2021 MSP430F5131

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      DA38
      2.      RSB40
      3.      YFF40
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BSL7
    2. 6.2  COMP10
    3. 6.3  CPU21
    4. 6.4  CPU22
    5. 6.5  CPU40
    6. 6.6  CPU46
    7. 6.7  CPU47
    8. 6.8  DMA4
    9. 6.9  DMA7
    10. 6.10 DMA10
    11. 6.11 EEM11
    12. 6.12 EEM17
    13. 6.13 EEM19
    14. 6.14 EEM21
    15. 6.15 EEM23
    16. 6.16 JTAG26
    17. 6.17 JTAG27
    18. 6.18 PMAP1
    19. 6.19 PMM14
    20. 6.20 PMM15
    21. 6.21 PMM18
    22. 6.22 PMM20
    23. 6.23 PMM26
    24. 6.24 PORT15
    25. 6.25 PORT19
    26. 6.26 PORT21
    27. 6.27 SYS12
    28. 6.28 SYS16
    29. 6.29 TD1
    30. 6.30 TD2
    31. 6.31 UCS9
    32. 6.32 UCS11
    33. 6.33 USCI26
    34. 6.34 USCI31
    35. 6.35 USCI34
    36. 6.36 USCI35
    37. 6.37 USCI39
    38. 6.38 USCI40
  7. 7Revision History

6.22 PMM20

PMM Module

Category

Functional

Function

Unexpected SVSL/SVML event during wakeup from LPM2/3/4 in fast wakeup mode

Description

If PMM low side is configured to operate in fast wakeup mode, during wakeup from LPM2/3/4 the internal VCORE voltage can experience voltage drop below the corresponding SVSL and SVML threshold (recommendation according to User's Guide) leading to an unexpected SVSL/SVML event. Depending on PMM configuration, this event triggers a POR or an interrupt.

Note: As soon the SVSL or the SVML is enabled in Normal performance mode the device is in slow wakeup mode and this erratum does not apply. In addition, this erratum has sporadic characteristic due to an internal asynchronous circuit. The drop of Vcore does not have an impact on specified device performance.

Workaround

If SVSL or SVML is required for application (to observe external disruptive events at Vcore pin) the slow wakeup mode has to be used to avoid unexpected SVSL/SVML events. This is achieved if the SVSL or the SVML is configured in "Normal" performance mode (not disabled and not in "Full" Performance Mode).