SLAZ246Z October 2012 – May 2021 MSP430F5131
TD Module
Functional
Timer halt on EXTCLR event
When the TEC module is configured to enable external asynchronous signals on the TECxCLR (TEC external clear) pin to clear the timer counter on the selected edge and the timer is halted after an external clear event but before next positive edge of the timer clock, then due to the erratum, it is not possible to write to the timer counter (TDxR) until the next positive timer clock edge occurrence. Halting of the timer right after an external clear event is possible if the system clock (MCLK) much greater than the Timer_D clock and the application halts the timer in the external clear interrupt service routine or if the application is doing random timer halts. This erratum does not cause any dead-lock conditions and the timer counter can be written into when the next positive timer clock edge is available.
If required to halt the timer and change the timer counter value on an external clear event, wait until one timer clock period has elapsed to change the timer counter value.