SLAZ105Z October   2012  – May 2021 CC430F6147

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  AES1
    5. 6.5  BSL7
    6. 6.6  BSL14
    7. 6.7  COMP10
    8. 6.8  CPU21
    9. 6.9  CPU22
    10. 6.10 CPU36
    11. 6.11 CPU40
    12. 6.12 CPU46
    13. 6.13 CPU47
    14. 6.14 DMA4
    15. 6.15 DMA7
    16. 6.16 DMA10
    17. 6.17 EEM17
    18. 6.18 EEM19
    19. 6.19 EEM23
    20. 6.20 JTAG26
    21. 6.21 JTAG27
    22. 6.22 LCDB5
    23. 6.23 LCDB6
    24. 6.24 PMM11
    25. 6.25 PMM12
    26. 6.26 PMM14
    27. 6.27 PMM15
    28. 6.28 PMM18
    29. 6.29 PMM20
    30. 6.30 PMM26
    31. 6.31 PORT15
    32. 6.32 PORT19
    33. 6.33 PORT29
    34. 6.34 RF1A1
    35. 6.35 RF1A2
    36. 6.36 RF1A3
    37. 6.37 RF1A5
    38. 6.38 RF1A6
    39. 6.39 RF1A8
    40. 6.40 SYS12
    41. 6.41 SYS16
    42. 6.42 UCS11
    43. 6.43 USCI26
    44. 6.44 USCI30
    45. 6.45 USCI34
    46. 6.46 USCI35
    47. 6.47 USCI39
    48. 6.48 USCI40
  7. 7Revision History

RF1A1

RF1A Module

Category

Functional

Function

The PLL lock detector output is not 100% reliable

Description

The PLL lock detector output is not 100% reliable and might toggle even if the PLL is in lock. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. The PLL is not in lock if the lock detector output is constantly logic low. It is not recommended to check for PLL lock by reading PKTSTATUS[0] with GDOx_CFG=0x0A or PKTSTATUS[2] register with GDOx_CFG=0x0A (x = 0 or 2).

Workaround

PLL lock can be checked reliably by these methods:
- Program register IOCFGx.GDOx_CFG=0x0A and use the lock detector output available on the GDOx pin as an interrupt for the MCU. A positive transition on the GDOx pin means that the PLL is in lock. It is important to disable for interrupt when waking the chip from SLEEP state as the wake-up might cause the GDOx pin to toggle when it is programmed to output the lock detector.
or
- Read register FSCAL1. The PLL is in lock if the register content is different from 0x3F.

With both of the above workarounds the CC1101 PLL calibration should be carried out with the correct settings for TEST0.VCO_SEL_CAL_EN and FSCAL2.VCO_CORE_H_EN. These settings are depending on the operating frequency, and is calculated automatically by SmartRF Studio.

Note that the TEST0 register content is not retained in SLEEP state, and thus it is necessary to write to this register as described
above when returning from the SLEEP state.