SLAU895A July   2023  – March 2026 TAS2572

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1  AC-MB Settings
      1. 2.1.1 Audio Serial Interface Settings
      2. 2.1.2 USB
      3. 2.1.3 External
    2. 2.2  AC-MB Power Supply
    3. 2.3  Default Jumper Setting on TAS2572EVM
    4. 2.4  I2C Target Address Selection
    5. 2.5  IOVDD and AVDD Power Supply Options on EVM
    6. 2.6  VBAT Power Supply for TAS2572 on EVM
      1. 2.6.1 VBAT 2S EVM Hardware Configuration
      2. 2.6.2 VBAT 3 S EVM Hardware Configuration
    7. 2.7  Speaker Outputs
    8. 2.8  1-Channel Configuration
    9. 2.9  4-Channel Configuration
    10. 2.10 4-Wire Measurement of Load
  9. 3Software
    1. 3.1 PurePath Console 3 Quick Startup
    2. 3.2 PPC3 - 257x EVM Feature Description
      1. 3.2.1 Limiter and Brown-Out Protection
      2. 3.2.2 Playback and PCM Configuration
      3. 3.2.3 TDM Receiver and Transmitter PPC3 Configuration
      4. 3.2.4 Miscellaneous and IRQZ Configuration
      5. 3.2.5 Tone Generator and Ultrasonic Chirp Generator
      6. 3.2.6 AVDD Bridge, Music Efficiency and Noise Gate
      7. 3.2.7 Boost and Channel Gain
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6Revision History

2.3 Default Jumper Setting on TAS2572EVM

Figure 4-1 given below illustrates all the default jumper settings for TAS2572EVM.

TAS2572EVM Default Jumper SettingsFigure 2-6 Default Jumper Settings

Table 4-1 shows the default positions for all the jumpers on TAS2572EVM.

Table 2-1 Default Jumper Settings

Jumper

Setting

Description

J7

Insert

IOVDD current sense for U1

J8

Insert

AVDD current sense for U1

J29

DNI

External VBST for U1

J6

Insert

VBAT pin current sense for U1

J93

Insert

SDOUT break for U1

J82

Insert

SDIN break for U1

J71

Insert

RST break for U1

J60

Insert

SBCLK break for U1

J50

Insert

FSYNC break for U1

J13

Insert

INT break for U1

J91

Insert

SDA break for U1

J92

Insert

SCL break for U1

J56

Insert (1-2)

VBAT source selector for U1

J28

Insert (2-3)

VBAT_SNS selector for U1

J39

Insert

VBAT source from barrel jack for U1

J46

Insert

VBAT source from barrel jack for U1

J34

Insert

IOVDD current sense for U2

J35

Insert

AVDD current sense for U2

J32

DNI

External VBST for U2

J33

Insert

VBAT pin current sense for U2

J97

Insert

SDOUT break for U2

J96

Insert

SDIN break for U2

J100

Insert

RST break for U2

J94

Insert

SBCLK break for U2

J95

Insert

FSYNC break for U2

J14

Insert

INT break for U2

J99

Insert

SDA break for U2

J98

Insert

SCL break for U2

J57

Insert (1-2)

VBAT source selector for U2

J52

Insert (2-3)

VBAT_SNS selector for U2

J41

Insert

VBAT source from barrel jack for U2

J49

Insert

VBAT source from barrel jack for U2

J74

DNI

EEPROM write protect

J51

DNI

EEPROM address selector

J37-4-9

IOVDD_MB

Buffer source selector

J38-5-2

IOVDD_MB

IOVDD source selector for U1 and U2

J36-11-10

IOVDD_MB

AVDD source selector for U1 and U2

J45

Insert (2-3)

1.8V LDO source selector

J19

Insert

I2C pull-up connect

J20

Insert

I2C pull-up connect

J77

DNI

FSYNC loopback for APx connection

J78

DNI

SBCLK loopback for APx connection